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Communication Processor Module

MOTOROLA

MPC823e REFERENCE MANUAL

16-155

SERIAL

I/F

COMMUNICATION

PROCESSOR MODULE

The pins available to the universal serial bus, serial communication controllers, and serial

management controllers in NMSI mode are illustrated in Figure 16-62.

The modem control pins for the USB in NMSI mode are as follows:

• USBRXD

• USBRXP

• USBTXP

• USBCLK ← BRG1–BRG4, CLK1–CLK4

• USBRXN

• USBTXN

•

USBOE

Figure 16-62. Bank of Clocks

SMC1

SMC2

SCC2

BRG1

BRG2

CLK2

SMCLK1

SMCLK2

RCLK2

TCLK2

BRGO1

BRGO2

BANK OF CLOCKS

SELECTION LOGIC

USB AND SCCS CONTROLLED IN THE SICR

SMCS CONTROLLED IN THE SIMODE REGISTER

CLK4

USBCLK

USB

CLOCK

BRG3

BRG4

BRGO3

SCC3

RCLK3

TCLK3

CLK1

CLK3

Main Page

Table of Contents3
List of Tables44
Features49
Section 1 Introduction49
Architecture54
- The Embedded Powerpc Core56
- The System Interface Unit56
- The Communication Processor Module57
- The Video/Lcd Controller58
  - The Video Controller58
  - The LCD Controller58
The PCMCIA-ATA Controller58
Power Management59
System Debug Support59
Applications59
Differences between MPC823 (Rev B) and Mpc823E60
Mpc823E Glueless System Design60
- External Signals62
The System Bus Signals63
- Memory Map77
- Reset89
Types of Reset90
- Power-On Reset90
- External Hard Reset91
- Internal Hard Reset91
- External Soft Reset92
- Internal Soft Reset92
  - Debug Port Soft Reset92
Reset Status Register93
How to Configure Reset95
- Hard Reset95
  - Hard Reset Configuration Word98
- Soft Reset100
  - Clocks and Power Control101
Features101
Register Model103
- System Clock and Reset Control Register103
- PLL, Low-Power, and Reset Control Register107
The Clock Module110
- On-Chip Oscillators and External Clock Input112
- System PLL112
  - SPLL Stability113
- The Low-Power Clock Divider114
- Internal Clock Signals116
- Clock Configuration122
  - Mode Clock Pins122
  - The System Phase-Locked Loop Pins123
Power Control124
- Power Rails124
- Keep-Alive Power125
  - Power Switching Example126
Low-Power Operation128
- The Powerpc Core132
Features132
Basic Structure of the Core133
- Instruction Flow Within the Core133
- Basic Instruction Pipeline135
Sequencer Unit135
- Flow Control136
- Issuing Instructions137
- Interrupts138
- Implementing the Precise Exception Model139
  - Restartability after an Interrupt141
- Processing an Interrupt142
- Serialization143
  - Latency143
- The External Interrupt144
  - Latency144
- Interrupt Ordering145
The Register Unit146
- Control Registers147
The Fixed-Point Unit155
- XER Update in Divide Instructions155
The Load/Store Unit156
- Issuing Load/Store Instructions157
- Serializing Load/Store Instructions158
- Instructions Issued to the Data Cache158
- Issuing Store Instruction Cycles158
- Issuing Nonspeculative Load Instructions158
- Executing Unaligned Instructions159
- Little-Endian Mode Support160
- Atomic Update Primitives160
- Instruction Timing161
- Stalling Storage Control Instructions161
- Accessing Off-Core Special Registers161
- Storage Control Instructions162
- Exceptions162
  - DAR, DSISR, and BAR Operation162
  - Powerpc Architecture Compliance163
Powerpc User Instruction Set Architecture (Book I)163
- Computation Modes163
- Reserved Fields163
- Classes of Instructions163
- Exceptions164
- The Branch Processor164
- Fetching Instructions164
- Branch Instructions164
  - Invalid Branch Instruction Forms164
  - Branch Prediction164
- The Fixed-Point Processor164
  - Move To/From System Register Instructions164
  - Fixed-Point Arithmetic Instructions165
- The Load/Store Processor165
Powerpc Virtual Environment Architecture (Book II)166
- Storage Model166
  - Memory Coherence166
  - Atomic Update Primitives166
- The Effect of Operand Placement on Performance167
- The Storage Control Instructions167
- Timebase168
Powerpc Operating Environment Architecture (Book III)168
- The Branch Processor168
- The Fixed-Point Processor168
  - Unsupported Registers168
  - Added Registers168
- Storage Model168
- Reference and Change Bits169
- Storage Protection169
- Storage Control Instructions169
- Interrupts169
- Timer Facilities179
- Optional Facilities and Instructions179
  - Instruction Execution Timing180
Instruction Timing List180
Instruction Execution Timing Examples183
- Data Cache Load183
- Writeback184
  - Writeback Arbitration184
  - Private Writeback Bus Load185
- Fastest External Load (Data Cache Miss)186
- A Full History Buffer187
- Branch Folding188
- Branch Prediction189
  - Instruction Cache190
Features190
Programming the Instruction Cache193
- Instruction Cache Control and Status Register194
- Instruction Cache Address Register195
- Instruction Cache Data Port Register196
Instruction Cache Operation196
- Instruction Cache Hit196
- Instruction Cache Miss197
- Instruction Fetch on a Predicted Path197
Instruction Cache Commands197
- Invalidating the Instruction Cache198
- Loading and Locking the Instruction Cache199
- Unlocking a Line199
- Unlocking the Entire Instruction Cache200
- Inhibiting the Instruction Cache200
- Instruction Cache Read201
- Instruction Cache Write203
Restrictions203
Instruction Cache Coherency203
Updating Code and Memory Region Attributes203
Reset Sequence203
Debug Support204
- Fetching Instructions from the Development Port204
  - Data Cache205
Features205
Organization of the Data Cache206
Programming the Data Cache207
- Powerpc Architecture Instructions207
- Implementation-Specific Operations208
- Special Registers of the Data Cache208
Operating the Data Cache214
- Data Cache Read214
- Data Cache Write214
  - Copyback Mode215
  - Writethrough Mode216
- Data Cache Inhibited Accesses216
- Data Cache Freeze216
- Data Cache Coherency217
Data Cache Commands217
- Flushing and Invalidating the Cache217
- Enabling and Disabling the Cache217
- Locking and Unlocking the Cache217
- Data Cache Instructions218
- Data Cache Read218
  - Memory Management Unit219
Features219
Address Translation220
- Translation Lookaside Buffer Operation220
Protection221
Storage Control222
Translation Table Structure223
- Level One Descriptor227
- Level Two Descriptor228
Programming the Memory Management Unit233
- Control Registers234
- MMU Data Content-Addressable Registers255
- MMU Instruction Content-Addressable Registers261
Interrupts265
- Implementation-Specific Instruction TLB Miss265
- Implementation-Specific Data TLB Miss265
- Implementation-Specific Instruction TLB Error266
- Implementation-Specific Data TLB Error266
Manipulating the Translation Lookaside Buffer267
- Reloading the Translation Lookaside Buffer267
  - Translation Reload Examples268
- Controlling the TLB Replacement Counter269
- Invalidating the Translation Lookaside Buffer269
- Loading the Reserved TLB Entries269
Requirements for Accessing the Memory Management Unit Control Registers270
- System Interface Unit271
Features272
System Configuration and Protection272
Interrupt Configuration275
- The Interrupt Structure275
- Priority of the Interrupt Sources276
- Programming the Interrupt Controller277
The Bus Monitor281
The Powerpc Decrementer282
- Decrementer Register283
The Powerpc Timebase284
- Timebase Register284
- Timebase Reference Registers285
- Timebase Status and Control Register286
The Real-Time Clock287
- Real-Time Clock Status and Control Register288
- Real-Time Clock Register289
- Real-Time Clock Alarm Seconds Register290
- Real-Time Clock Alarm Register291
The Periodic Interrupt Timer292
- Periodic Interrupt Status and Control Register293
- Periodic Interrupt Timer Count Register294
- Periodic Interrupt Timer Register295
The Software Watchdog Timer296
- Software Service Register297
Freeze Operation298
- Low-Power Stop Operation298
Multiplexing the System Interface Unit Pins299
Programming the System Interface Unit300
- System Configuration and Protection Registers300
Features308
Transfer Signals308
- Control Signals310
Bus Signal Descriptions311
Bus Interface Operation314
- Basic Transfers315
- Single Beat Transfers315
  - Single Beat Read Flow316
  - Single Beat Write Flow319
- Burst Transfers323
- The Burst Mechanism323
- Transfer Alignment and Packaging332
- Arbitration Phase-Related Signals334
- Address Transfer Phase-Related Signals338
- Data Transfer Phase-Related Signals343
  - Data Signal343
- Termination Phase-Related Signals343
- Storage Reservation Protocol345
- Exception Control Cycles348
  - RETRY Signal349
    - Endian Modes354
Little-Endian Features356
Big-Endian System Features358
Powerpc Little-Endian System Features358
Setting the Endian Mode of Operation358
- Memory Controller359
Features359
Architecture362
Register Model365
- Register Descriptions367
  - Base Registers367

Motorola MPC823e - Page 609

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