Communication Processor Module
16-176
MPC823e REFERENCE MANUAL
MOTOROLA
SCCs
COMMUNICATION
16
PROCESSOR MODULE
ENT—Enable Transmit
This bit enables the transmitter hardware state machine for a serial communication
controller. When ENT is cleared, the transmitter is disabled. If ENT is cleared during
transmission, the transmitter aborts the current character and the TXDx pin returns to the
idle state. Data already in the transmit shift register is not transmitted. ENT can be set or
cleared, regardless of whether the serial clocks are present. Refer to
Section 16.9.14 Disabling the SCCs On-the-Fly
for a description of how to properly
disable and reenable a serial communication controller.
MODE—Channel Protocol Mode
0000 = HDLC.
0001 = Reserved.
0010 = AppleTalk/LocalTalk.
0011 = SS7. Reserved for RAM microcode.
0100 = UART.
0101 = Profibus. Reserved for RAM microcode.
0110 = ASYNC HDLC/IrDA.
0111 = V.14. Reserved for RAM microcode.
1000 = Reserved.
1001 = DDCMP. Reserved for RAM microcode.
1010 = Reserved.
1011 = Reserved.
1100 = Ethernet.
11xx = Reserved.
16.9.3 Protocol-Specific Mode Register
The functionality of each serial communication controller varies according to the protocol
selected in the MODE field of the GSMR_L. Each serial communication controller has an
additional 16-bit, memory-mapped, read/write protocol-specific mode register (PSMR) that
configures it for a particular mode. Since every SCCx protocol has specific requirements,
the PSMR bits are different for each protocol.
Note:
The serial communication controller that controls transmission provides other
tools besides the ENT bit. These tools include the
STOP TRANSMIT
command,
GRACEFUL STOP TRANSMIT
command,
RESTART TRANSMIT
command,
the freeze option in UART mode, CTSx
flow control option in UART mode, and
the R bit of the transmit buffer descriptor.
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