Motorola MPC823e - Page 646

Communication Processor Module
16-192 MPC823e REFERENCE MANUAL MOTOROLA
SCCs
COMMUNICATION
16
PROCESSOR MODULE
Reception delays are determined by the CDx pin as illustrated in Figure 16-69. If the CDS
bit in the GSMR_H is zero, then the CDx
pin is sampled on the rising receive clock edge
prior to data being received. If the CDS bit in the GSMR_H is 1, then the CDx
pin transitions
cause data to be immediately gated into the receiver.
If the CDx pin is programmed to envelope the data, it must remain asserted during frame
transmission or a CDx
lost error occurs. Negation of the CDx pin terminates reception. If the
CDS bit in the GSMR_H is zero, the CDx
pin must be sampled by a serial communication
controller before a CDx
lost error is recognized. Otherwise, the negation of CDx immediately
causes the CDx
lost condition to occur.
Figure 16-69. Using CDx
to Control Synchronous Protocol Reception
Note: If the CDS bit in the GSMR_H is set, all CDx transitions must occur while the
receive clock is low.
FIRST BIT OF DATA IN FRAME LAST BIT OF FRAME DATA
RXDx
CDx
FIRST BIT OF FRAME DATA
LAST BIT OF FRAME DATA
RCLK
(INPUT)
CDx SAMPLED LOW HERE
(INPUT)
CDx SAMPLED HIGH HERE
RCLK
RXDx
(INPUT)
CDx
(INPUT)
CDx ASSERTION IMMEDIATELY
GATES RECEPTION
CDx NEGATION IMMEDIATELY
HALTS RECEPTION
NOTES:
1. CDS is set to 1 in the GSMR and CDP is set to 0.
2. If CDx is negated prior to the last bit of the receive frame, CDx lost is signaled in the frame buffer descriptor.
3. If CDP is set to 1, CDx lost cannot occur and CDx negation has no effect on reception.
NOTES:
1. CDS is set to 0 in the GSMR and CDP is set to 0.
2. If CDx is negated prior to the last bit of the receive frame, CDx lost is signaled in the frame buffer descriptor.
3. If CDP is set to 1, CDx lost cannot occur and CDx negation has no effect on reception.