Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-197
SCCs
COMMUNICATION
16
PROCESSOR MODULE
• Manchester—A one is represented by a high to low transition at the center of the bit. A
zero is represented by a low to high transition at the center of the bit. In both cases there
may be a transition at the beginning of the bit to set up the level required to make the
correct center transition.
• Differential Manchester—A one is represented by a transition at the center of the bit
with the opposite direction from the transition at the center of the preceding bit. A zero
is represented by a transition at the center of the bit with the same polarity from the
transition at the center of the preceding bit.
16.9.12 Clock Glitches
A clock glitch occurs when an input clock signal transitions between a one and zero state
two times, in a time period small enough to violate the minimum high or low time
specification of the input clock. They also occur when excessive noise is present on a slowly
rising or falling signal.
This can be a potential problem for many communication systems. Not only can glitched
clocks cause systems to experience errors, but they can also cause undetected errors.
Systems that supply an external clock to a serial channel are often susceptible to glitches
caused by noise, connecting or disconnecting the physical cable from the application board,
or excessive ringing on a clock line.
The serial communication controllers have special circuits designed to detect glitches that
occur within the system. Glitches that could cause a serial communication controller to
transition to the wrong state. This status information can be used to alert the system of a
problem at the physical layer. The glitch detect circuit is not a specification test, so if you
develop a circuit that does not meet the input clocking specifications for a serial
communication controller, erroneous data can be received or transmitted that is not
indicated by the glitch detection logic. Conversely, if a glitch indication is signaled, it does
not guarantee that erroneous data was received or transmitted. Regardless of whether the
DPLL is used, the received clock is passed through a noise filter that eliminates any noise
spikes that affect a single sample. This sampling is enabled using the GDE bit of the
GSMR_H.
If a spike is detected, a maskable receive or transmit glitched clock interrupt is generated in
the event register of the SCCx channel. Although you can either reset the SCCx receiver or
transmitter or continue operation, the statistics on clock glitches must be kept for later
evaluation. The glitch status indication can also be used as a debugging aid during the early
phases of prototype testing.
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