Motorola MPC823e - Page 717

Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-263
COMMUNICATION
16
PROCESSOR MODULE
SCCs
16.9.17.2.3 Using the Time-Slot Assigner. Sometimes the HDLC bus can be used in a
configuration that has a local HDLC bus and a time-division multiplex transmission line that
is not an HDLC bus. Figure 16-88 illustrates such a case. The local HDLC bus controllers
all communicate over time-slots. However, more than one HDLC bus controller is assigned
to a given time-slot and the HDLC bus protocol controls access during that time-slot.
Figure 16-87. Delayed RTSx Mode
Figure 16-88. HDLC Bus Time-Slot Assigner Transmission Line Configuration
TCLK
TXDx
CTSx
RTSx
COLLISION
1ST BIT
2ND BIT
3RD BIT
RTSx ACTIVE FOR ONLY
2 BIT TIMES
HDLC BUS
CONTROLLER
L1TXDx
L1RXDx
A
NOTES:
1. All TX pins of slave devices should be configured to open-drain in the port C parallel I/O port.
2. The TSA in the serial interface of each station is used to configure the preferred time-slot.
3. You can choose the number of stations to share a time-slot. In this example, two are used.
RX
TX
LOCAL HDLC BUS
STATIONS SHARE TIME-SLOT N STATIONS SHARE TIME-SLOT M
R
+5
CTSx
HDLC BUS
CONTROLLER
L1TXDx
L1RXDx
B
CTSx
HDLC BUS
CONTROLLER
L1TXDx
L1RXDx
C
CTSx
HDLC BUS
CONTROLLER
L1TXDx
L1RXDx
D
CTSx
LINE
DRIVER