Communication Processor Module
16-300 MPC823e REFERENCE MANUAL MOTOROLA
COMMUNICATION
16
SCCs
16.9.20.5.5 High-Speed IrDA Programming Example. High-speed infrared
programming is very similar to SCC2 Transparent programming. The parameter RAM
programming and the RX buffer descriptor and TX buffer descriptor are the same as in the
SCCx transparent mode, which is described in Section 16.9.21 The SCCx in Transparent
Mode. The SCC2 and infrared registers must be initialized. The following list is an
initialization sequence for a high-speed infrared channel. The transmitter and receiver are
both enabled. Both transmit and receive clocks are provided externally to MPC823e using
the CLK3 pin.
1. Configure the port A pins to enable the TXD2 and RXD2 pins. Write PAPAR bits 13
and 12 with ones. Write PADIR bits 13 and 12 with zeros. Write PAODR bits 13 and
12 with zeros.
2. Configure port A to enable the CLK3 pin. Write PAPAR bit 5 with a one. Write PADIR
bit 5 with a zero.
3. Connect the CLK3 pin to the SCC2 using the serial interface. In the SICR, write 110
to the R2CS and T2CS fields.
4. Connect the SCC2 to the NMSI (its own set of pins). Clear the SC2 bit in the SICR.
5. Write the SDCR with the appropriate arbitration ID.
6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RX buffer
descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of dual-port RAM, and one TX buffer descriptor following
that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.
7. Program the CPCR to execute the INIT RX AND TX PARAMS command for the
SCC2.
8. Write RFCR and TFCR with 0x18 for normal operation.
9. Write the maximum number of bytes per receive buffer to the MRBLR. For this case,
assume 16 bytes, so MRBLR equals 0x0010.
10.Write 0xFFFFFFFF to CRC_P for 32-bit CRC-CCITT (CRC32). For details, see
Section 16.9.21.5 SCCx Transparent Parameter RAM Memory Map.
11.Write 0xDEBB20E3 to CRC_C for 32-bit CRC-CCITT (CRC32).
12.Initialize the RX buffer descriptor. Assume the RX data buffer is at 0x00001000 in main
memory. Write 0xB000 to RX_BD_Status. Write 0x0000 to RX_BD_Length (not
required because it is only done for instructional purposes). Write 0x00001000 to
RX_BD_Pointer.
13.Initialize the TX buffer descriptor. Assume the TX data buffer is at 0x00002000 in main
memory and contains five 8-bit characters. Write 0xBC00 to TX_BD_Status. Write
0x0005 to TX_BD_Length. Write 0x00002000 to TX_BD_Pointer.
14.Write 0xFFFF to the SCCE–Transparent to clear any previous events.
15.Write 0x0013 to the SCCM–Transparent to enable the TXE, TX, and RX interrupts.
16.Write 0x20000000 to the CIMR to allow SCC2 to generate a system interrupt. The
CICR must also be initialized.
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