Communication Processor Module
16-302 MPC823e REFERENCE MANUAL MOTOROLA
COMMUNICATION
16
SCCs
If just one of the TTX or TRX bits is set, the other half of a serial communication controller
operates with another protocol as programmed in the MODE field of the GSMR_L. This
allows loopback modes to DMA data from one memory location to another while converting
the data to a specific serial format. The SCCx in Transparent mode can work with the
time-slot assigner or nonmultiplexed serial interface and support modem lines with the
general-purpose I/O pins. The data can be transmitted and received with the MSB or LSB
first in each octet.
The SCCx in Transparent mode consists of separate transmit and receive sections whose
operations are asynchronous with the core. Each clock can be supplied from the internal
baud rate generator bank, DPLL output, or external pins.
16.9.21.1 FEATURES. The following list summarizes the main features of the SCCx in
Transparent mode:
• Flexible data buffers
• Automatic Sync detection on reception
• CRCs can be transmitted and received
• Reverse data mode
• Another protocol can be performed on the other half of the SCCx in Transparent mode
16.9.21.2 SCCx TRANSPARENT CHANNEL FRAME TRANSMISSION PROCESS. The
transparent transmitter is designed to work with almost no intervention from the core and
when the core enables the SCCx transmitter in transparent mode, it starts transmitting idles.
The serial communication controllers poll the first buffer descriptor in the channel’s transmit
(TX) buffer descriptor table. When there is a message to transmit, the serial communication
controllers fetch the data from memory, loads the transmit FIFO, and waits for transmitter
synchronization before transmitting the message.
Transmitter synchronization can be achieved with the CTSx
pin or by waiting for the receiver
to achieve synchronization, depending on how the TXSY bit is set in the GSMR_H. Once
transmitter synchronization is achieved, transmission begins.
When buffer descriptor data has been completely transmitted, the L bit is checked and if it
is set, the serial communication controllers write the message status bits into the buffer
descriptor and clear the R bit. They then start transmitting idles until the next buffer
descriptor is ready and if it is ready some idles are still transmitted. The transmitter only
begins transmission again after it achieves synchronization. When the end of the current
buffer descriptor has been reached and the L bit is cleared, only the R bit is cleared and the
transmitter moves immediately to the next buffer to begin transmission with no gap on the
serial line between buffers. Failure to provide the next buffer in time results in a transmit
underrun, thus causing the TXE bit in the SCCE–Transparent register to be set.
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