Motorola MPC823e - Page 767

Communication Processor Module
MOTOROLA MPC823e REFERENCE MANUAL 16-313
COMMUNICATION
16
PROCESSOR MODULE
SCCs
R—Ready
0 = The data buffer associated with this buffer descriptor is not ready for transmission.
You are free to manipulate this buffer descriptor or its associated data buffer. The
communication processor module clears this bit after the buffer is transmitted or
after an error condition is encountered.
1 = The data buffer, which you have prepared for transmission, is not transmitted yet
or is currently being transmitted. You cannot write any fields of this buffer descriptor
once this bit is set.
Bits 1 and 7–13—Reserved
These bits are reserved and must be set to 0.
W—Wrap (Final Buffer Descriptor in Table)
0 = This is not the last buffer descriptor in the TX buffer descriptor table.
1 = This is the last buffer descriptor in the TX buffer descriptor table. After this buffer is
used, the communication processor module receives incoming data into the first
buffer descriptor that TBASE points to in the table. The number of TX buffer
descriptors in this table is programmable and determined only by the W bit and
overall space constraints of the dual-port RAM.
I—Interrupt
0 = No interrupt is generated after this buffer is serviced.
1 = When this buffer is serviced by the communication processor module, the TX or
TXE bit is set in the SCCE–Transparent register. These bits can cause interrupts
if they are enabled.
L—Last in Message
0 = The last byte in the buffer is not the last byte in the transmitted transparent frame.
Data from the next transmit buffer is transmitted immediately after the last byte of
this buffer.
1 = The last byte in the buffer is the last byte in the transmitted transparent frame. After
this buffer is transmitted, the transmitter must be synchronized before the next
buffer is transmitted.
TC—Transmit CRC
0 = No CRC sequence is transmitted after this buffer.
1 = A frame check sequence that is defined by the TCRC field in the GSMR_H is
transmitted after the last byte of this buffer.
CM—Continuous Mode
0 = Normal operation.
1 = The R bit is not cleared by the communication processor module after this buffer
descriptor is closed, thus allowing the associated data buffer to be automatically
retransmitted next time the communication processor module accesses this buffer
descriptor. However, the R bit is cleared if an error occurs during transmission,
regardless of how the CM bit is set.