Motorola MPC823e - Page 78

Memory Map
3-2 MPC823e REFERENCE MANUAL MOTOROLA
MEMORY MAP
3
09C POR3—PCMCIA Interface Option Register 3 32 17-17
0A0 PBR4—PCMCIA Interface Base Register 4 32 17-16
0A4 POR4—PCMCIA Interface Option Register 4 32 17-17
0A8 PBR5—PCMCIA Interface Base Register 5 32 17-16
0AC POR5—PCMCIA Interface Option Register 5 32 17-17
0B0 PBR6—PCMCIA Interface Base Register 6 32 17-16
0B4 POR6—PCMCIA Interface Option Register 6 32 17-17
0B8 PBR7—PCMCIA Interface Base Register 7 32 17-16
0BC POR7—PCMCIA Interface Option Register 7 32 17-17
0C0 to 0E3 RES—Reserved — —
0E4 PGCRB—PCMCIA Interface General Control Register B 32 17-15
0E8 PSCR—PCMCIA Interface Status Change Register 32 17-11
0EC to 0EF RES—Reserved — —
0F0 PIPR—PCMCIA Interface Input Pins Register 32 17-9
0F4 to 0F7 RES—Reserved — —
0F8 PER—PCMCIA Interface Enable Register 32 17-13
0FC to 0FF RES—Reserved — —
MEMORY CONTROLLER
100 BR0—Base Register Bank 0 32 15-9
104 OR0—Option Register Bank 0 32 15-11
108 BR1—Base Register Bank 1 32 15-9
10c OR1—Option Register Bank 1 32 15-11
110 BR2—Base Register Bank 2 32 15-9
114 OR2—Option Register Bank 2 32 15-11
118 BR3—Base Register Bank 3 32 15-9
11C OR3—Option Register Bank 3 32 15-11
120 BR4—Base Register Bank 4 32 15-9
124 OR4—Option Register Bank 4 32 15-11
128 BR5—Base Register Bank 5 32 15-9
12C OR5—Option Register Bank 5 32 15-11
130 BR6—Base Register Bank 6 32 15-9
134 OR6—Option Register Bank 6 32 15-11
Table 3-1. MPC823e Internal Memory Map (Continued)
INTERNAL
ADDRESS REGISTER
SIZE
(IN BITS)
PAGE NUMBER
LOCATION