Reset
4-6
MPC823e REFERENCE MANUAL
MOTOROLA
RESET
4
SWRS—Software Watchdog Reset Status
This bit is cleared by a power-on reset. When a software watchdog expire event occurs, this
bit is set and remains that way until the software clears it. The SWRS bit can be negated by
writing a 1, but a write of zero has no effect on it.
0 = No software watchdog reset event occurred.
1 = A software watchdog reset event occurred.
CSRS—Check Stop Reset Status
This bit is cleared by a power-on reset. When the core enters the checkstop state and the
checkstop reset is enabled by the CSR bit in the PLPRCR, this bit is set and remains that
way until the software clears it. The CSRS bit can be negated by writing a 1, but a write of
zero has no effect on it.
0 = No enabled checkstop reset event occurred.
1 = An enabled checkstop reset event occurred.
DBHRS—Debug Port Hard Reset Status
This bit is cleared by a power-on reset. When the debug port hard reset request is set, this
bit is set and remains that way until the software clears it. The DBHRS bit can be negated
by writing a 1, but a write of zero has no effect on it.
0 = No debug port hard reset request occurred.
1 = A debug port hard reset request occurred.
DBSRS—Debug Port Soft Reset Status
This bit is cleared by a power-on reset. When the debug port soft reset request is set, this
bit is set and remains that way until the software clears it. The DBSRS bit can be negated
by writing a 1, but a write of zero has no effect on it.
0 = No debug port soft reset request occurred.
1 = A debug port soft reset request occurred.
JTRS—JTAG Reset Status
This bit is cleared by a power-on reset. When the JTAG reset request is set, this bit is set
and remains that way until the software clears it. The JTRS bit can be negated by writing a
1, but a write of zero has no effect on it.
0 = No JTAG reset event occurred.
1 = A JTAG reset event occurred.
Bits 8–31—Reserved
These bits are reserved and must be set to 0.
To Next Page
Loading...
