Panasonic MN101L Series

Chapter 3
Interrupts
III - 6 Overview
 Interrupt Level and Priority
The LSI provides three levels of interrupt priority, and the lower vector number has priority when several inter-
rupts with the same interrupt priority level occur. (For example, when the vector 3 and the vector 4 are set to the
priority of level 1 and those interrupt trigger occur simultaneously, the interrupt of the vector 3 is accepted.)
Maskable interrupts are accepted when LV1-0 is less than PSW.IM1-0. NMI is handled in priority to maskable
interrupts.
Figure:3.1.3 Interrupt Priority Example
Table:3.1.2 Relation between PSW.IM1-0 and acceptable interrupts
Mask Level PSW.IM1-0 Priority Acceptable Interrupt
IM1 IM0
Level 0 0 0 Highest NMI
Level 1 0 1 : NMI, Maskable Interrupt of Level 0
Level 2 1 0 : NMI, Maskable Interrupt of Level 0 to 1
Level 3 1 1 Lowest NMI, Maskable Interrupt of Level 0 to 2
Level1
Level2
Vector 1 (Non-maskable interrupt)
Vector 2, 5, 6
Vector 3, 4
Vector 7
Priority Interrupt Vector No.
Vector 1
Vector 2
Vector 5
Vector 6
Vector 3
Vector 4
Vector 7
Level0
Interrupt level setting range
1
2
3
4
5
6
7