Chapter 3
Interrupts
Overview III - 7
Determination of Maskable Interrupt Acceptance
The procedures of the interrupt acceptance is described below.
1. IR is set to "1".
2. When IE is "1", the interrupt request is sent to CPU.
3. When LV1-0 is less than PSW.IM1-0 and PSW.MIE is "1", the above interrupt request is accepted.
4. IR is cleared to "0" by hardware. (IE is not cleared by hardware.)
Figure:3.1.4 Determination of Interrupt Acceptance
..
After IR is set to “1” by an interrupt trigger at step 1, if the same interrupt trigger occurs during
the time of above 2 - 4 steps, the latter interrupt trigger is ignored.
..
7
xICR
VF
IM1BKD IM0
NF
SW
In the case of xICR.LV1-0 < PSW.IM1-0,
the interrupt is accepted.
IRIE
LV1
ZFCF
MIE
LV0
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