Chapter 3
Interrupts
Overview III - 13
The following figure shows the processing sequence when the higher priority level interrupt occurs while process-
ing the lower priority level interrupt.
(Interrupt 1: LV1-0 = "10", Interrupt 2: LV1-0 = "00")
Figure:3.1.7 Processing Sequence for Multiple Interrupts
Interrupt 1 occurs
(LV1-0="10")
Main Program
PSW.IM1-0="11"
Interrupt handler: 1
Interrupt handler: 2
RTI
IM1-0="10"
MIE="1"
Interrupt 2 occurs
(LV1-0="00")
Accepted because MIE = "1" and LV1-0 < IM1-0
IM1-0="00"
)(
IM1-0="11"
)(
(
IM1-0="10"RTI
Accepted because LV1-0 < IM1-0
Restart interrupt handler: 1
Interrupt acceptance cycle
Interrupt acceptance cycle
Parentheses () indicates hardware processing.
(
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