Panasonic MN101L Series

Chapter 9
16-bit Timer
16-bit Timer Control Registers IX - 13
 Timer 7 Mode Register 4 (TM7MD4: 0x03F9E)
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The TM7MD4.T7CAPCLR is valid when the timer is in active. Note that the binary counter is
not cleared when capturing data while the timer is stopped.
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Set the Timer 7 mode registers while the TM7MD1.TM7EN is "0". And the TM7MD1.TM7EN
must not be changed at the same time as the other bit.
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bp7654 3210
Bit name - - -
T7ONE
SHOT
T7NODED - T7ICT2
T7CAP
CLR
At reset0000 0000
Access R R R R/W R/W R R/W R/W
bp Bit name Description
7-5 - Always read as 0.
4T7ONESHOT
Select pulse
0: Continuous pulse
1: One-shot pulse
3T7NODED
Set dead time
0: Yes
1: No
2 - Always read as 0.
1T7ICT2
Select capture trigger
0: Timer 0 interrupt
1: Timer 1 interrupt
0T7CAPCLR
Binary counter clear enable at capture
0: Disabled (not cleared)
1: Enabled (cleared)