Panasonic MN101L Series

Chapter 9
16-bit Timer
IX - 48 16-bit Standard IGBT Output (with Variable Duty)
 Count timing of Standard IGBT Output (Normal) (Timer 7)
Figure:9.9.1 Count timing of Standard IGBT Output (Normal)
(A) Once the IGBT trigger is input, the IGBT operation is valid at the next clock. After the IGBT operation
becomes valid, the IGBT output holds "Low" until the next count clock.
(B) While the IGBT trigger is valid and the binary counter counts up from "0x0000" to the TM7OC2 compare
match, the IGBT output is "High".
(Only for the 1st cycle of counting, the output is "High" from"0x0001".)
(C) After the TM7OC2 compare match, the output changes to "Low" and the binary counter continues counting
up until it overflows.
(D) When the binary counter overflows, the IGBT output returns to "High".
(E) When the IGBT trigger becomes invalid, the timer is initialized and the IGBT output is forced to be "Low".
N
N+1 N+2 FFFE
FFFF
C
ount
c
lock
T
M7EN
b
it
C
ompare
r
egister 1
B
inary
c
ounter
0000 0001
0002
00000000 0001 N-1
N
T
M7IO output
(
IGBT output)
I
GBT
t
rigger
(A)
(B) (C) (D) (E)