Chapter 13
Serial Interface
XIII - 16 Control Registers
SCIFn (n = 2, 3) Mode Register 2 (SC2MD2, SC3MD2)
bp7 6 543 2 1 0
Bit name SCnFDC1 SCnFDC0 SCnRSTN - SCnCKPH SCnSBCSEN SCnSBCSLV -
Initial value 0 0 0 0 0 0 0 0
Access R/W R/W R/W R R/W R/W R/W R
bp Bit name Description
7-6 SCnFDC1-0
Output level selection after the final bit of SBOn is transmitted
00: Fixed at "1" (High) output
01: Hold the final data
10: Fixed at "0" (Low) output
11: Setting prohibit
5 SCnRSTN
Serial reset control
0:Reset
1:Reset release
4 - "0" is always read out.
3 SCnCKPH
Clock phase selection
(Selectable only in Clock-Synchronous communication,
always set "0" in IIC communication.)
0: Data transmission at leading edge, data reception at trailing edge
1: Data reception at leading edge, data transmission at trailing edge
2
SCnSBCSE
N
SBCSn function selection
(Selectable only in Clock-Synchronous communication,
always set "0" in IIC communication.)
0: Disabled
1: Enabled (Chip select I/O)
1 SCnSBCSLV
SBCSn polarity selection
(Selectable only in Clock-Synchronous communication, and always set "0" in IIC
communication.)
0: Active-low
1: Active-high
0 - "0" is always read out.
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