Panasonic MN101L Series - Page 405

Chapter 13
Serial Interface
Control Registers XIII - 17
 SCIFn (n = 0, 1) Mode Register 3 (SC0MD3, SC1MD3)
bp76543210
Bit name SCnFDC1 SCnFDC0 SCnRSTN SCnRSRN SCnCKPH
SCnSBCS
EN
SCnSBCS
LV
-
Initial
value
00000000
Access R/W R/W R/W R/W R/W R/W R/W R
bp Bit name Description
7-6 SCnFDC1-0
Output level selection after the final bit of SBOn is transmitted
00: Fixed at "1" (High) output
01: Hold the final data
10: Fixed at "0" (Low) output
11: Setting prohibit
5 SCnRSTN
Serial reset control in Clock-Synchronous communication
0: Reset
1: Reset release
Serial reset control in UART transmission
0: Reset
1: Reset release
4 SCnRSRN
Always set to "0 in Clock-Synchronous communication
Serial reset control in UART reception
0: Reset
1: Reset release
3 SCnCKPH
Clock phase selection
(Selectable only in Clock-Synchronous communication,
Always set "0" in IIC communication.)
0: Data transmission at leading edge, data reception at trailing edge
1: Data reception at leading edge, data transmission at trailing edge
2 SCnSBCSEN
SBCSn function selection
(Selectable only in Clock-Synchronous communication,
Always set "0" in UART communication.)
0: Disabled
1: Enabled (Chip select I/O)
1 SCnSBCSLV
SBCSn polarity selection
(Selectable only in Clock-Synchronous communication,
Always set "0" in UART communication.)
0: Active-low
1: Active-high
0 - "0" is always read out.