Chapter 13
Serial Interface
XIII - 32 Clock-Synchronous Communication
Setting of Clock Pin (SBTn)
Figure:13.3.1 shows the relation among SBTn level at bus-idle (serial communication is not executed), active
edge of SBTn at data transmission/reception and SCnMD0.SCnCE1, SCnMD3.SCnCKPH (n = 0, 1), and
SCnMD2.SCnCKPH (n = 2, 3).
"Leading edge" represents the first edge of square wave when communication is started. "Trailing edge" repre-
sents the inverted edge of "Leading edge". For example, when SBTn during non-communication is "High", the
first falling edge after the start of communication is "Leading edge" and the inverted rising edge is "Trailing
edge".
Table:13.3.1 Clock Edge of Data Transmission and Reception
Figure:13.3.6 and Figure:13.3.7 show the 3-wire communication waveform when SCnCKPH = 0.
Figure:13.3.6 3-wire Communication Transmission/ Reception Timing
(When SCnCKPH = 0 and SCnCE1 = 0)
SCnCE1 SCnCKPH
SBTn status during
non-communication
Clock edge in data
transmission
Clock edge in data reception
0 0 "High" Leading edge (falling) Trailing edge (rising)
0 1 "High" Trailing edge (rising) Leading edge (falling)
1 0 "Low" Leading edge (rising) Trailing edge (falling)
1 1 "Low" Trailing edge (falling) Leading edge (rising)
SBT pin
SBI pin
SBO pin
Data is sent in synchronization with the falling edge of the clock.
Data is received in synchronization with the rising edge of clock.
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