Panasonic MN101L Series

Chapter 13
Serial Interface
Clock-Synchronous Communication XIII - 33
Figure:13.3.7 3-wire Communication Transmission/ Reception Timing
(When SCnCKPH = 0 and SCnCE1 = 1)
Figure:13.3.8 shows the 4-wire communication waveform when SCnCKPH = 1. Data are received at a leading
edge and transferred at a trailing edge. Conversely, During 4-wire communication when SCnCKPH = 0, data are
received at a trailing edge and transferred at a leading edge as shown in Figure:13.3.9.
In master communication, a transfer clock is output from SBTn after the time of 0.5 transfer clock (0.5 T) has
elapsed since SBCSn was asserted. In slave communication, input a transfer clock to SBTn after the time of 0.5
transfer clock (0.5 T) has elapsed since SBCSn was asserted.
The last bit data output hold time of transmission data is different depending on the value of SCnCKPH. (Refer to
Figure:13.3.8 and Figure:13.3.9.) Allow adequate 1-T time for the last bit of reception data to hold data.
Figure:13.3.8 4-wire Communication Transmission/ Reception Timing (SCnCKPH = 1)
Data is received in synchronization with the falling edge of the clock.
Data is sent in synchronization with the rising edge of the clock.
SBT pin
SBI pin
SBO pin
SBTn
SBIn reception timing
SBOn
SBCSn
(At master)
SBOn
(At slave)
(At master(output))
(At slave(input))
SBCSn
(SCnCE1 = 0)
SBTn
(SCnCE1 = 1)
T
Last bit data hold period
(= 1T)
0.5T(minimum value)