Chapter 13
Serial Interface
XIII - 38 Clock-Synchronous Communication
Communication in CPU STANBY Mode
In CPU STANBY mode, a communication complete interrupt of slave reception can make CPU operation mode
return from CPU STANBY mode to NORMAL mode. Read reception data in RXBUFn after the return to NOR-
MAL mode.
Before CPU operation mode becomes NORMAL mode, write data to TXBUFn as an activation source. While in
communication during STANBY mode, be sure to set SCnCTM and SCnCKPH bits to 0.
..
When the reception with STANDBY mode in SDIF0/SCIF1, set SCnMD0.SCnCTM and
SCnMD3.SCnCKPH to 0. If they are not set to 0, SCIFn does not work properly.
..
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When the reception with STANDBY mode in SDIF2/SCIF3, set SCnMD0.SCnCTM and
SCnMD2.SCnCKPH to 0. If they are not set to 0, SCIFn does not work properly.
..
..
A transfer clock can be input after a time of 3.5 transfer clocks has elapsed since the activa-
tion source with a data write to TXBUFn occurred. So, change CPU operation mode to
STANDBY mode after that.
..
Figure:13.3.10 Reception Timing in STANDBY mode
(Reception: at rising edge)
T
Waiting stable oscillation
Standby mode
Normal mode
Normal mode
SBO/SBI
Communication
completion interrupt
(Set data to TXBUFn)
SBTn
SCnRBSY
Twait(=3.5T)
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