Chapter 14
DMA Controller
XIV - 8 DMA Controller Control Registers
DMA Control Register 1 upper side (DMCTR1H: 0x03E03)
bp76543210
Bit name---DMOVF---DMRQF
At reset00000000
AccessRRRRRRRR
bp Bit name Description
7-5 - Always read as "0".
4DMOVF
DMA-Error detection
When the DMA-Error occurs, the DMOVF is set to "1".
The DMOVF is cleared to "0" by writing DMCTR1L.DMTEN.
0: Not Detect
1: Detect
3-1 - Always read as "0".
0DMRQF
DMA Busy monitor
The DMRQF is set to "1" when the DMA start trigger occurs.
In the case of the single transfer, the DMRQF is cleared to "0" at the end of single data transfer.
In the case of the burst transfer, the DMRQF is cleared to "0" at the end of the last burst data transfer.
0: Not Busy
1: Busy
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