Chapter 14
DMA Controller
DMA Controller Control Registers XIV - 7
DMA Control Register 1 lower side (DMCTR1L: 0x03E02)
bp76543210
Bit name-------DMTEN
At reset00000000
AccessRRRRRRRR/W
bp Bit name Description
7-1 - Always read as "0".
0DMTEN
DMA transfer enable control
After the DMTEN is set, DMA waits for the DMA start trigger to occur.
(When the software trigger is selected in DMCTR0L.DMBG4-0, DMA transfer starts immediately after the
DMTEN is set to "1".)
When the last data is transferred, the DMTEN is cleared to "0" by hardware. Setting the DMTEN to "0"
during DMA transfer makes the transfer finished, which is called "Emergency stop".
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