Panasonic MN101L Series

Chapter 16
A/D Converter (ADC)
XVI - 10 Operation
16.3.1 Setup
 Input Pins of A/D Conversion Setup
Input pins for ADC is selected by the ANCTR1.ANCHS2-0.
 A/D Conversion Clock Setup
The A/D conversion clock is set by the ANCTR0.ANCK2-0.
Set the A/D conversion cycle (T
ADCLK
) between 750 ns and 100 µs. Table:16.3.1 shows the machine clock
(HCLK, SCLK, SYSCLK) and the A/D conversion cycle (T
ADCLK
). (calculated as f
SYSCLK
= f
HCLK
/2, f
SCLK
)
Table:16.3.1 A/D Conversion Clock and A/D Conversion Cycle
 A/D Conversion Sample hold Time (T
S
) Setup
The sample hold time of A/D conversion is set with the ANCTR0.ANSH1-0.
The sample hold time of A/D conversion depends on the external circuit, so set the appropriate value based on the
analog input impedance.
Table:16.3.2 Sample Hold Time of A/D Conversion and A/D Conversion Time
ANCK2-0
A/D
conversion clock
A/D conversion cycle (T
ADCLK
)
f
HCLK
= 10 MHz f
SCLK
= 32.768 kHz
000 SYSCLK/2
400 ns
(Setting is prohibited.)
61.035 µs
001 SYSCLK/3
600 ns
(Setting is prohibited.)
91.552 µs
010 SYSCLK/4 800 ns
122.070 µs
(Setting is prohibited.)
011 SYSCLK/6 1.2 µs
183.105 µs
(Setting is prohibited.)
100 SYSCLK/8 1.6 ns
244.140 µs
(Setting is prohibited.)
101 SYSCLK/12 2.4 µs
366.210 µs
(Setting is prohibited.)
110 SYSCLK/16 3.2 µs
488.281 µs
(Setting is prohibited.)
111 SCLK - 30.517 µs
ANSH1-0
Sample hold
clock
A/D conversion cycle (T
AD
)
00
T
ADCLK
× 2T
ADCLK
× (18 + 2) + 3 × 1 / f
SYSCLK
01
T
ADCLK
× 6T
ADCLK
× (18 + 6) + 3 × 1 / f
SYSCLK
10
T
ADCLK
× 18 T
ADCLK
× (18 + 18) + 3 × 1 / f
SYSCLK
11 - -