S3F84B8_UM_REV 1.00 11 8-BIT TIMER A
11-4
NOTE: When the counter clear bit(.5) is set, the 8-bit counter is cleared and
it will be cleared automatically.
Timer A Control Register (TACON)
E4H, Set1, Bank1, R/W, Reset: 00H
LSBMSB.7.6.5.4.3.2.1.0
Timer A match/capture interrupt
enable bit:
0 = Disable interrupt
1 = Enable interrrupt
Timer A operating mode selection bit:
00 = Interval mode (TAOUT mode)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF interrupt and match
interrupt can occur)
Timer A start/stop bit:
0 = Stop timer A
1 = Start timer A
Timer A overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrrupt
Timer A counter clear bit:
0 = No effect
1 = Clear the timer A counter
(when write)
Timer A match Interrupt pending bit:
0 = No pending (clear pending bit when write)
1 = Interrupt pending
Timer A OVF Interrupt pending bit:
0 = No pending (clear pending bit when write)
1 = Interrupt pending
Figure 11-1 Timer A Control Register (TACON)
To Next Page
