Samsung S3F84B8 - Page 4

Table of Contents
1 OVERVIEW OF S3F84B8 MICROCONTROLLER......................................1-1
1.1 S3C8-Series Microc
ontrollers .................................................................................................................. 1-1
1.1.1 S3F84B8 Mic
rocontroller .................................................................................................................. 1-1
1.1.2 Key Features of S3F84B8
................................................................................................................ 1-2
1.1.3 Block Diagram of S3F84B8
.............................................................................................................. 1-5
1.1.4 Pin As
signments............................................................................................................................... 1-6
1.1.5 Pin Desc
riptions................................................................................................................................ 1-7
1.1.6 Pin Circuits
........................................................................................................................................ 1-9
2 ADDRESS SPACES....................................................................................2-1
2.1 Overview of Addres
s Spaces................................................................................................................... 2-1
2.2 Internal Program Memory (ROM)
............................................................................................................ 2-2
2.2.1 Smart Option
..................................................................................................................................... 2-3
2.3 Register Arc
hitecture ............................................................................................................................... 2-4
2.3.1 Register Page Pointer (PP)
.............................................................................................................. 2-6
2.3.1.1 Register Set 1
......................................................................................................................... 2-7
2.3.1.2 Register Set 2
......................................................................................................................... 2-7
2.3.1.3 Prime Register Space ............................................................................................................. 2-8
2.3.1.4 Working Regis
ters................................................................................................................... 2-9
2.3.2 Using The Regis
ter Points (RP) ..................................................................................................... 2-10
2.4 Register Address
ing............................................................................................................................... 2-12
2.4.1 Common Working Regis
ter Area (C0H–CFH)................................................................................ 2-14
2.4.2 4-Bit Working Regis
ter Addressing................................................................................................. 2-15
2.4.3 8-Bit Working Regis
ter Addressing................................................................................................. 2-17
2.4.4 System and User Stack
.................................................................................................................. 2-19
2.4.4.1 Stack Operations
................................................................................................................... 2-19
2.4.4.2 User-defined Stacks
.............................................................................................................. 2-19
2.4.4.3 Stack Pointers
(SPL, SPH) ................................................................................................... 2-19
3 ADDRESSING MODES ...............................................................................3-1
3.1 Overview of Addressi
ng Modes ............................................................................................................... 3-1
3.2 Register (R) Addres
sing Mode................................................................................................................. 3-2
3.3 Indirect Register (IR) Address
ing Mode................................................................................................... 3-3
3.4 Indirect Register (IR) Address
ing Mode (Continued)............................................................................... 3-4
3.5 Indirect Register (IR) Address
ing Mode (Continued)............................................................................... 3-5
3.6 Indirect Register (IR) Address
ing Mode (Concluded) .............................................................................. 3-6
3.7 Indexed (X) Addressing Mode
................................................................................................................. 3-7
3.8 Indexed (X) Addressing Mode (Continued)
............................................................................................. 3-8
3.9 Indexed (X) Addressing Mode (Concluded)
............................................................................................. 3-9
3.10 Direct Address
(DA) Mode ................................................................................................................... 3-10
3.11 Direct Address (DA) Mode
(Continued) ............................................................................................... 3-11
3.12 Indirect Address
(IA) Mode .................................................................................................................. 3-12
3.13 Relative Address
(RA) Mode ............................................................................................................... 3-13
3.14 Immediate Mode (IM)
........................................................................................................................... 3-14
4 CONTROL REGISTERS..............................................................................4-1