Samsung S3F84B8 - Page 5

4.1 Overview of Control Registers ................................................................................................................. 4-1
4.1.1 ADCON — A/D Converter Control Regis
ter: FAH, BANK0.............................................................. 4-5
4.1.2 AMTDATA — Anti-mis-trigger Data Regis
ter: F6H, BANK0............................................................. 4-6
4.1.3 BTCON — Basic Timer Control Regis
ter: D3H, BANK0 .................................................................. 4-6
4.1.4 BUZCON — BUZ Control Regis
ter: F7H, BANK0............................................................................ 4-7
4.1.5 CLKCON — Clock Control Regis
ter: D4H, BANK0.......................................................................... 4-8
4.1.6 CMP0CON — Comparator0 Control Regis
ter: EAH, BANK0 .......................................................... 4-9
4.1.7 CMP1CON — Comparator1 Control Regis
ter: EBH, BANK0 ........................................................ 4-10
4.1.8 CMP2CON — Comparator1 Control Regis
ter: ECH, BANK0 ........................................................ 4-11
4.1.9 CMP3CON — Comparator1 Control Regis
ter: EDH, BANK0 ........................................................ 4-12
4.1.10 CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK0
.................................... 4-13
4.1.11 FLAGS — System Flags
Register: D5H, BANK0......................................................................... 4-14
4.1.12 FMCON — Flash Memory Control Regis
ter: F5H, BANK1 .......................................................... 4-15
4.1.13 FMSECH — Flash Memory Sec
tor Address Register (High Byte): F7H, BANK1........................ 4-15
4.1.14 FMSECL — Flash Memory Sector Address
Register (Low Byte): F8H, BANK1 ......................... 4-16
4.1.15 FMUSR — Flash Memory User Programmi
ng Enable Register: F6H, BANK1............................ 4-16
4.1.16 IMR — Interrupt Mask Regis
ter: DDH, BANK0 ............................................................................ 4-17
4.1.17 IPH — Instruction Pointer (High Byte): DAH, BANK0
.................................................................. 4-18
4.1.18 IPL — Instruction Pointer (Low Byte): DBH, BANK0
.................................................................... 4-18
4.1.19 IPR — Interrupt Priority Regis
ter: FFH, BANK0 ........................................................................... 4-19
4.1.20 IRQ — Interrupt Request Regi
ster: DCH, BANK0........................................................................ 4-20
4.1.21 OPACON — OP AMP Control Regis
ter: E0H, BANK1 ................................................................ 4-21
4.1.22 P0CONH — Port 0 Control Register (High Byte): E4H, Bank0
.................................................... 4-22
4.1.23 P0CONL — Port 0 Control Register (Low Byte): E5H, BANK0
.................................................... 4-23
4.1.24 P0INT — Port 0 Interrupt Control Regis
ter: E3H, BANK0............................................................ 4-24
4.1.25 P0PND — Port 0 Interrupt Pendi
ng Register: E6H, BANK0 ........................................................ 4-25
4.1.26 P1CON — Port 1 Control Regis
ter: E7H, BANK0 ........................................................................ 4-26
4.1.27 P2CONH — Port 2 Control Register (High Byte): E8H, BANK0
.................................................. 4-27
4.1.28 P2CONL — Port 2 Control Register (Low Byte): E9H, BANK0
.................................................... 4-28
4.1.29 PWMCON — PWM Control Regis
ter: EFH, BANK0 .................................................................... 4-29
4.1.30 PWMCCON — PWM CMP Control Regis
ter: F0H, BANK0......................................................... 4-30
4.1.31 PWMDL — Comparator0 Output Delay Regis
ter: F5H, Bank0.................................................... 4-31
4.1.32 PP — Register Page Pointer: DFH, BANK0
................................................................................. 4-31
4.1.33 RESETID — Reset Source Indic
ating Register: F2H, BANK1..................................................... 4-32
4.1.34 RP0 — Register Pointer 0: D6H, BANK0
.................................................................................. 4-33
4.1.35 RP1 — Register Pointer 1: D7H, BANK0
..................................................................................... 4-33
4.1.36 SPL — Stack Pointer: D9H, BANK0
............................................................................................. 4-34
4.1.37 STOPCON — STOP Mode Control Register: F4H, BANK1
........................................................ 4-34
4.1.38 SYM — System Mode Regi
ster: DEH, BANK0 ............................................................................ 4-35
4.1.39 TACON — Timer A Control Register: E1H, BANK1
..................................................................... 4-36
4.1.40 TAPS — TA Pre-scalar Regis
ter: E2H, BANK1 ........................................................................... 4-37
4.1.41 TCCON — Timer C
Control Register: E5H, BANK1 .................................................................... 4-38
4.1.42 TCPS — TC Pre-scalar Regis
ter: E6H, BANK1........................................................................... 4-39
4.1.43 TDCON — Timer D
Control Register: E9H, BANK1 .................................................................... 4-40
4.1.44 TDPS — TD Pre-scalar Regis
ter: EAH, BANK1 .......................................................................... 4-41
5 INTERRUPT STRUCTURE..........................................................................5-1
5.1 Overview of Interrupt Struc
ture................................................................................................................ 5-1
5.1.1 Levels
............................................................................................................................................... 5-1
5.1.2 Vectors.............................................................................................................................................. 5-1
5.1.3 Sources............................................................................................................................................. 5-1
5.1.4 Interrupt Types
.................................................................................................................................. 5-2