Samsung S3F84B8 - Page 6

5.1.5 S3F84B8 Interrupt Structure............................................................................................................. 5-3
5.1.5.1 Interrupt Vec
tor Addresses ..................................................................................................... 5-4
5.1.5.2 Enable/Disable Interrupt Instructions (EI, DI).......................................................................... 5-4
5.1.6 System-Level Interrupt Control Regis
ters ........................................................................................ 5-5
5.1.7 Interrupt Proces
sing Control Points.................................................................................................. 5-6
5.1.8 Peripheral Interrupt Control Regis
ters.............................................................................................. 5-7
5.1.9 System Mode Regi
ster (SYM) .......................................................................................................... 5-8
5.1.10 Interrupt Mask Regis
ter (IMR) ........................................................................................................ 5-9
5.1.11 Interrupt Priority Regis
ter (IPR) .................................................................................................... 5-10
5.1.12 Interrupt Request Regis
ter (IRQ).................................................................................................. 5-12
5.1.13 Interrupt Pending F
unction Types ................................................................................................ 5-13
5.1.13.1 Overview of Interrupt Pending
Function Types................................................................... 5-13
5.1.13.2 Pending Bits Cleared Automatic
ally by the Hardware ........................................................ 5-13
5.1.13.3 Pending Bits Cleared by the S
ervice Routine..................................................................... 5-13
5.1.14 Interrupt Source Polling Sequence
............................................................................................... 5-14
5.1.15 Interrupt Servic
e Routines ............................................................................................................ 5-14
5.1.16 Generating Interrupt Vec
tor Addresses........................................................................................ 5-15
5.1.17 Nesting of Vec
tored Interrupts...................................................................................................... 5-15
5.1.18 Instruction Pointer (I
P).................................................................................................................. 5-16
5.1.19 Fast Interrupt Proces
sing ............................................................................................................. 5-16
5.1.20 Procedure for Initiating Fas
t Interrupts ......................................................................................... 5-17
5.1.21 Fast Interrupt Service Routine
...................................................................................................... 5-17
5.1.22 Relationship to Interrupt Pending Bit Types
................................................................................. 5-17
5.1.23 Programming Guidelines
.............................................................................................................. 5-17
6 INSTRUCTION SET.....................................................................................6-1
6.1 Overview of Ins
truction Set ...................................................................................................................... 6-1
6.1.1 Key Features of Ins
truction Set ........................................................................................................ 6-1
6.1.1.1 Data Types
.............................................................................................................................. 6-1
6.1.1.2 Register Addressing................................................................................................................ 6-1
6.1.1.3 Addres
sing Modes .................................................................................................................. 6-1
6.2 Flags Register (FLAGS)
........................................................................................................................... 6-5
6.2.1 Flag Des
criptions.............................................................................................................................. 6-6
6.2.2 Instruction Set Notation
.................................................................................................................... 6-7
6.2.3 Condition Codes
............................................................................................................................. 6-11
6.3 Instruction Descriptions.......................................................................................................................... 6-12
6.3.1 ADC — Add with Carry
................................................................................................................... 6-13
6.3.2 ADD — Add
.................................................................................................................................... 6-14
6.3.3 AND — Logical AND
...................................................................................................................... 6-15
6.3.4 BAND — Bit AND
........................................................................................................................... 6-16
6.3.5 BCP — Bit Compare
....................................................................................................................... 6-17
6.3.6 BITC — Bit Complement
................................................................................................................ 6-18
6.3.7 BITR — Bit Res
et ........................................................................................................................... 6-19
6.3.8 BITS — Bit Set
................................................................................................................................ 6-20
6.3.9 BOR — Bit OR
................................................................................................................................ 6-21
6.3.10 BTJRF — Bit Test, Jump Relativ
e on False................................................................................. 6-22
6.3.11 BTJRT — Bit Test, J
ump Relative on True .................................................................................. 6-23
6.3.12 BXOR — Bit XOR
......................................................................................................................... 6-24
6.3.13 CALL — Call Proc
edure ............................................................................................................... 6-25
6.3.14 CCF — Complement Carry Flag
.................................................................................................. 6-26
6.3.15 CLR — Clear
................................................................................................................................ 6-27
6.3.16 COM — Complement
................................................................................................................... 6-28