Schweitzer Engineering Laboratories SEL-787 - Page 539

J.11
Date Code 20081022 Instruction Manual SEL-787 Relay
Relay Word Bits
Definitions
SCnnQU SELOGIC Counters 17 through 24 asserted when counter = preset value. 66
SCnnQU SEL
OGIC Counters 25 through 32 asserted when counter = preset value. 68
SG1 Asserts when setting group 1 is active. 33
SG2 Asserts when setting group 2 is active. 33
SG3 Asserts when setting group 3 is active. 33
SG4 Asserts when setting group 4 is active. 33
SV01–SV08 SEL
OGIC control equation variables SV01 through SV08. 50
SV01T–SV08T SEL
OGIC control equation variable SV01T through SV08T with settable pickup and dropout
time delay.
51
SV09–SV16 SEL
OGIC control equation variables SV09 through SV16. 52
SV09T–SV16T SEL
OGIC control equation variable SV09T through SV16T with settable pickup and dropout
time delay.
53
SV17–SV24 SEL
OGIC control equation variables SV17 through SV24. 54
SV17T–SV24T SEL
OGIC control equation variable SV17T through SV24T with settable pickup and dropout
time delay.
55
SV25–SV32 SEL
OGIC control equation variables SV25 through SV32. 56
SV25T–SV32T SEL
OGIC control equation variable SV25T through SV32T with settable pickup and dropout
time delay.
57
T01_LED–T06_LED SEL
OGIC control equation: drives T01_LED through T06_LED. 40
TFLTALA Through fault alarm, phase A. 41
TFLTALB Through fault alarm, phase B. 41
TFLTALC Through fault alarm, phase C. 41
TH5 Fifth Harmonic alarm threshold exceeded. 17
TH5T Fifth Harmonic alarm threshold exceeded for longer than TH5D. 6
TMBnA Channel A transmit mirror bits TMB1A through TMB8A. 71
TMBnB Channel B transmit mirror bits TMB1B through TMB8B. 73
TQUAL1 Time Quality Bit, add 1 when asserted. 105
TQUAL2 Time Quality Bit, add 2 when asserted. 105
TQUAL4 Time Quality Bit, add 4 when asserted. 105
TQUAL8 Time Quality Bit, add 8 when asserted. 105
TR1 Trip SEL
OGIC control equation TR1 (Also has been referred to as TRIPEQ1). 34
TR2 Trip SEL
OGIC control equation TR2 (Also has been referred to as TRIPEQ2). 34
TREA1 Trigger Reason Bit 1 for synchrophasors. 33
TREA2 Trigger Reason Bit 2 for synchrophasors. 33
TREA3 Trigger Reason Bit 3 for synchrophasors. 33
TREA4 Trigger Reason Bit 4 for synchrophasors. 33
TRGTR Target Reset. Asserts for one quarter-cycle when you execute a front-panel, serial port target
reset command, or Modbus target reset.
28
TRIP Trip Logic Output. 19
TRIP1 Trip1 Logic Output. 34
TRIP2 Trip2 Logic Output. 34
TRIPXFMR TripXFMR Logic Output. 34
TRXFMR Trip SEL
OGIC control equation TRXFMR (Also has been referred to as TRXFMREQ). 34
Table J.2 Relay Word Bit Definitions for the SEL-787 (Sheet 8 of 9)
Bit Definition Row