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TMS320C28x
Texas Instruments TMS320C28x User Manual
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Register Operations
6-17
C28x Assembly Language Instructions
T
able 6
−
2.
Register Operations (Continued)
Mnemonic
Page
Description
Miscellaneous Operations (Continued)
ESTOP0
Emulation Stop 0
6-93
ESTOP1
Emulation Stop 1
6-94
173
175
Table of Contents
1 Architectural Overview
3
Read this First
3
Table of Contents
9
1.1 Introduction to the CPU
20
Compatibility with Other TMS320 Cpus
20
Compatibility Modes
20
Switching to C28X Mode from Reset
21
1.2 Components of the CPU
22
Central Processing Unit (CPU)
22
Emulation Logic
22
High-Level Conceptual Diagram of the CPU
22
Emulation Logic
23
Signals
24
1.3 Memory Map
25
On-Chip Program/Data
25
Reserved
25
CPU Interrupt Vectors
25
Tms320C28X High-Level Memory Map
26
1.4 Memory Interface
27
Address and Data Buses
27
Special Bus Operations
28
Summary of Bus Use During Data-Space and Program-Space Accesses
28
Special Bus Operations
29
Alignment of 32-Bit Accesses to Even Addresses
29
2 Central Processing Unit
31
Status Register ST0
31
2.1 CPU Architecture
32
Conceptual Block Diagram of the CPU
33
2.2 CPU Registers
34
CPU Register Summary
34
Accumulator (ACC, AH, AL)
36
C28X Registers
36
Individually Accessible Portions of the Accumulator
37
Available Operations for Shifting Values in the Accumulator
38
Multiplicand Register (XT)
38
Individually Accessible Halves of the P Register
39
Individually Accessible Halves of the XT Register
39
Product Register (P, PH, PL)
39
Data Page Pointer (DP)
40
Product Shift Modes
40
Pages of Data Memory
41
Stack Pointer (SP)
41
Address Reach of the Stack Pointer
42
Auxiliary Registers (XAR0−XAR7, AR0−AR7)
42
XAR0 − XAR7 Registers
43
Interrupt-Control Registers (IFR, IER, DBGIER)
44
Program Counter (PC)
44
Return Program Counter (RPC)
44
Status Registers (ST0, ST1)
44
Status Register (ST0)
46
Bit Fields of Status Register (ST0)
46
Instructions that Affect OVC/OVCU
47
Instructions Affected by the PM Bits
50
Instructions Affected by V Flag
51
Negative Flag under Overflow Conditions
54
Bits Affected by the C Bit
55
Instructions that Affect the TC Bit
61
Instructions Affected by SXM
63
2.4 Status Register ST1
64
Bit Fields of Status Register 1 (ST1)
64
2.5 Program Flow
69
Instruction Pipeline
70
Multiply Operations
71
Conceptual Diagram of Components Involved in 16 X16-Bit Multiplication
72
Conceptual Diagram of Components Involved in 32 X 32-Bit Multiplication
73
Shift Operations
74
Shift Operations
75
3 CPU Interrupts and Reset
81
CPU Interrupts Overview
82
CPU Interrupt Vectors and Priorities
84
Interrupt Vectors and Priorities
85
Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT
86
Interrupt Flag Register (IFR)
87
Requirements for Enabling a Maskable Interrupt
87
CPU Interrupt Enable Register (IER) and CPU Debug Interrupt Enable Register (DBGIER)
88
Interrupt Enable Register (IER)
89
Standard Operation for Maskable Interrupts
91
Standard Operation for CPU Maskable Interrupts
92
Register Pairs Saved and SP Positions for Context Saves
94
Register Pairs Saved and SP Positions for Context Saves
95
Typical ISR
96
Nonmaskable Interrupts
97
Functional Flow Chart for an Interrupt Initiated by the TRAP Instruction
98
Hardware Interrupt NMI
101
Illegal-Instruction Trap
102
Registers after Reset
103
Hardware Reset (RS)
103
4 Pipeline
107
Pipelining of Instructions
108
Decoupled Pipeline Segments
110
Address Counters FC, IC, and PC
111
Relationship between Pipeline and Address Counters FC, IC, and PC
112
Visualizing Pipeline Activity
113
Diagramming Pipeline Activity
114
Simplified Diagram of Pipeline Activity
115
Freezes in Pipeline Activity
116
Pipeline Protection
118
Protection against Register Conflicts
119
Register Conflict
120
Avoiding Unprotected Operations
122
Write Followed by Read Protection Mode
123
5 C28X Addressing Modes
125
Types of Addressing Modes
126
Addressing Modes for "Loc16" or "Loc32
128
Addressing Modes Select Bit (AMODE)
128
Assembler/Compiler Tracking of AMODE Bit
131
Direct Addressing Modes (DP)
132
Stack Addressing Modes (SP)
133
Indirect Addressing Modes
134
C2Xlp Indirect Addressing Modes (ARP, XAR0 to XAR7)
136
Circular Indirect Addressing Modes (XAR6, XAR1)
145
Circular Buffer with AMODE
146
Circular Buffer with AMODE
148
Register Addressing Modes
149
Bit Register Addressing Modes
150
Data/Program/Io Space Immediate Addressing Modes
152
Program Space Indirect Addressing Modes
154
Byte Addressing Modes
155
Alignment of 32-Bit Operations
157
Instruction Set Summary (Organized by Function)
158
Instruction Set Summary (Organized by Function)
159
6.2 Register Operations
161
Diagnostics and Recovery
554
Overview of Emulation Features
555
JTAG Header to Interface a Target to the Scan Controller
556
Debug Interface
556
Pin Header Signal Descriptions
557
Selecting Device Operating Modes by Using TRST, EMU0, and EMU1
558
Debug Terminology
559
Execution Control Modes
560
Stop Mode Execution States
561
Real-Time Mode
562
Real-Time Mode Execution States
563
Summary of Stop Mode and Real-Time Mode
564
Stop Mode Versus Real-Time Mode
565
Interrupt Handling Information by Mode and State
566
Aborting Interrupts with the ABORTI Instruction
568
DT-DMA Mechanism
569
Process for Handling a DT-DMA Request
570
Analysis Breakpoints, Watchpoints, and Counter(S)
572
Benchmark Counter/Event Counter(S)
573
Typical Analysis Unit Configurations
574
Data Logging
576
ADDRL (at Data-Space Address 00 083816)
578
ADDRH (at Data-Space Address 00 083916)
578
Start Address and DMA Registers
578
REFL (at Data-Space Address 00 084A16)
579
REFH (at Data-Space Address 00 084B16 )
579
End-Address Registers
579
Accessing the Emulation Registers Properly
579
Data Log Interrupt (DLOGINT)
580
Examples of Data Logging
581
Initialization Code for Data Logging with End Address
582
Valid Combinations of Analysis Resources
583
Analysis Resources
583
Sharing Analysis Resources
583
Diagnostics and Recovery
584
A.2 Register Figures
586
Reset Values of the Status and Control Registers
587
A−1. Status Register ST0
589
Status Register ST1, Bits15−8
590
Status Register ST1, Bits 7−0
591
Interrupt Flag Register (IFR
592
Interrupt Enable Register (IER)
593
A−6. Debug Interrupt Enable Register (DBGIER)
594
B.1 Introduction
595
TMS320 ROM Code Prototype and Production Flowchart
597
B.2 Code Submission
598
B.3 ROM Layout
599
B.4 ROM Code Generation Flow
600
Checksum Computation Memory Locations
601
C.1 Summary of Architecture Differences between C2Xlp and C28X
603
General Features
604
Register Changes from C2Xlp to C28X
605
C.2.1 CPU Register Changes
606
Xar0 − Xar7
606
C.2.2 Data Page (DP) Pointer Changes
607
Direct Addressing Mode Mapping
608
Status Register Comparison between C2Xlp and C28X
609
C28X Product Mode Shifter
610
C2Xlp Product Mode Shifter
610
Reset Conditions of Internal Registers
612
Status Register Bits
613
C.3 Memory Map
614
Memory Map Comparison (See Note A)
615
B0 Memory Map
616
D.1 Introduction
617
D.2 Recommended Migration Flow
619
Flow Chart of Recommended Migration Steps
620
D.3 Mixing C2Xlp and C28X Assembly
622
Code to Disable an Interrupt
623
Code to Save Contents of IMR (IER) and Disabling Lower Priority Interrupts at Beginning of ISR
623
D.4 Code Examples
623
Code to Clear the IFR Register
624
Code to Enable an Interrupt
624
D.4.3 Context Save/Restore
624
Full Context Save/Restore Comparison
625
C2Xlp and C28X Differences in Interrupts
626
D.5 Reference Tables for C2Xlp Code Migration Topics
626
C2Xlp and C28X Differences in Status Registers
627
C2Xlp and C28X Differences in Memory Maps
628
C2Xlp and C28X Differences in Instructions and Registers
629
D−10. Code Generation Tools and Syntax Differences
631
E.1 Condition Tests on Flags
633
C28X and C2Xlp Flags
634
C2Xlp Instructions and C28X Equivalent Instructions
635
E.2 C2Xlp Vs. C28X Mnemonics
635
E.3 Repeatable Instructions
641
Repeatable Instructions for the C2Xlp and C28X
641
F.1 Architecture Changes
644
C28X Registers
645
F.1.1 Changes to Registers
645
F−2. Full Context Save/Restore
645
ST0 Register Bits
646
ST1 Register Bits
647
F.1.2 Full Context Save and Restore
648
Code for a Full Context Save/Restore for C28X Vs C27X
649
F.1.3 B0/B1 Memory Map Consideration
649
C27X Compatible Mapping of Blocks M0 and M1
650
Mapping of Memory Blocks B0 and B1 on C27X
650
Building a C27X Object File from C27X Source
651
F.1.4 C27X Object Compatibility
651
Building a C28X Object File from Mixed C27X/C28X Source
652
F.2 Moving to a C28X Object
652
F.3 Migrating to C28X Object Code
654
Instruction Syntax Change
655
F.3.2 Repeatable Instructions
656
F.3.3 Changes to the SUBCU Instruction
657
F−8. Compiling C28X Source
659
Debug Interrupt Enable Register (DBGIER)
665
4
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Texas Instruments TMS320C28x Specifications
General
Brand
Texas Instruments
Model
TMS320C28x
Category
Processor
Language
English
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