Register Operations
6-16
Table 6−2. Register Operations (Continued)
Mnemonic PageDescription
Status Register Operations (ST0, ST1) (Continued)
CLRC
ZAP
OVC
OVC
Clear OVC bits
Clear overflow counter
6-70
6-395
DINT Disable maskable interrupts (set INTM bit) 6-85
EINT Enable maskable interrupt (clear INTM bit) 6-92
MOV PM,AX Load product shift mode bits PM = AX(2:0) 6-179
MOV OVC,loc16 Load the overflow counter 6-176
MOVU OVC,loc16 Load overflow counter with unsigned value 6-222
MOV loc16,OVC Store the overflow counter 6-173
MOVU loc16,OVC Store the unsigned overflow counter 6-221
SETC Mode Set multiple status bits 6-320
SETC XF Set XF bit and output signal 6-324
SETC
C28MAP
M0M1MAP Set M0M1MAP bit
Set the M0M1MAP bit
6-65
6-322
SETC
C28OBJ
OBJMODE Set OBJMODE bit
Set the OBJMODE bit
6-66
6-323
SETC
LPADDR
AMODE Set AMODE bit
Alias for SETC AMODE 6-129
SPM PM Set product shift mode bits 6-327
Miscellaneous Operations
ABORTI Abort interrupt 6-18
ASP Align stack pointer 6-52
EALLOW Enable access to protected space 6-90
IDLE Put processor in IDLE mode 6-98
NASP Un-align stack pointer 6-243
NOP {*ind} No operation with optional indirect address modification 6-250
ZAPA Zero accumulator P register and OVC 6-396
EDIS
Disable access to protected space 6-91
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