Register Operations
6-15C28x Assembly Language Instructions
Table 6−2. Register Operations (Continued)
Mnemonic PageDescription
Branch/Call/Return Operations (Continued)
XCALL pma,COND C2XLP source-compatible conditional call 6-376
XCALL pma,*,ARPn C2XLP source-compatible call with ARP modification 6-375
XCALL *AL C2XLP source-compatible indirect call 6-374
XRET Alias for XRETC UNC 6-391
XRETC COND C2XLP source-compatible conditional return 6-392
Interrupt Register Operations
AND IER,#16bit Bitwise AND to disable specified CPU interrupts 6-46
AND IFR,#16bit Bitwise AND to clear pending CPU interrupts 6-47
IACK #16bit Interrupt acknowledge 6-97
INTR INT1/../INT14
NMI
EMUINT
DLOGINT
RTOSINT
Emulate hardware interrupts 6-114
MOV IER,loc16 Load the interrupt-enable register 6-163
MOV loc16,IER Store interrupt enable register 6-172
OR IER,#16bit Bitwise OR 6-260
OR IFR,#16bit Bitwise OR 6-261
TRAP #0..31 Software trap 6-363
Status Register Operations (ST0, ST1)
CLRC Mode Clear status bits 6-72
CLRC XF Clear the XF status bit and output signal 6-71
CLRC
C28ADDR
AMODE Clear the AMODE bit
Clear the AMODE status bit
6-67
6-64
CLRC
C27OBJ
OBJMODE Clear the OBJMODE bit
Clear the OBJMODE bit
6-69
6-63
CLRC
C27MAP
M0M1MAP Clear the M0M1MAP bit
Set the M0M1MAP bit
6-68
6-62
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