IMACL P,loc32,*XAR7/++
6-101
On the C28x devices, memory blocks are mapped to both program and
data space (unified memory), hence the ”*XAR7/++” addressing mode
can be used to access data space variables that fall within the program
space address range. With some addressing mode combinations, you can
get conflicting references. In such cases, the C28x will give the
“loc16/loc32” field priority on changes to XAR7.
For example:
IMACL P,*−−XAR7,*XAR7++ ; −−XAR7 given priority
IMACL P,*XAR7++,*XAR7 ; *XAR7++ given priority
IMACL P,*XAR7,*XAR7++ ; *XAR7++ given priority
Flags and
Z
After the addition, the Z flag is set if the ACC value is zero, else Z is cleared.
Modes
N
After the addition, the N flag is set if bit 31 of the ACC is 1, else N is cleared.
C
If the addition generates a carry, C is set; otherwise C is cleared.
V
If an overflow occurs, V is set; otherwise V is not affected.
OVCU
The overflow counter is incremented when the addition operation gener-
ates an unsigned carry. The OVM mode does not affect the OVCU counter.
PM
The value in the PM bits sets the shift mode that determines which portion
of the lower 38 bits of the 64-bit results are stored in the P register.
Repeat This instruction is repeatable. If the operation follows a RPT instruction,
then it will be executed N+1 times. The state of the Z, N, C and OVC flags
will reflect the final result in the ACC. The V flag will be set if an intermedi-
ate overflow occurs in the ACC.
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