LSL64 ACC:P,#1..16
6-137
LSL64 ACC:P,#1..16 Logical Shift Left
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
LSL64 ACC:P,#1..16 0101 0110 1010 SHFT 1 − 1
Operands ACC:P Accumulator register (ACC) and product register (P)
#1..16 Shift value
Description Logical shift left the 64-bit combined value of the ACC:P registers by the
amount specified in the shift value field. During the shift, the low order bits are
zero-filled and the last bit shifted out is stored in the carry bit flag:
0
C
ACC:P
ACC:P
Last bit out
Discard other bits
Left shift
(Immediate value)
Flags and
Modes
N After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the
N bit is set; otherwise N is cleared.
Z After the shift, the Z flag is set if the combined 64-bit value of the ACC:P is
zero; otherwise, Z is cleared.
C The last bit shifted out of the combined 64-bit value is loaded into the C bit.
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Logical shift left the 64-bit Var64 by 10:
MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64
MOVL P,@Var64+0 ; Load P with low 32 bits of Var64
LSL64 ACC:P,#10 ; Logical shift left ACC:P by 10
MOVL @Var64+2,ACC ; Store high 32-bit result into Var64
MOVL @Var64+0,P ; Store low 32-bit result into Var64
To Next Page
Loading...