LSL64 ACC:P,T
6-138
LSL64 ACC:P,T 64-Bit Logical Shift Left by T(5:0)
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
LSL64 ACC:P,T 0101 0110 0101 0010 1 − 1
Operands ACC:P Accumulator register (ACC) and product register (P)
T Upper 16 bits of the multiplicand register (XT)
Description Logical shift left the 64-bit combined value of the ACC:P registers by the
amount specified in the six least significant bits of the T register,
T(5:0) = 0…63. Higher order bits are ignored. During the shift, the low order
bits are zero-filled. If T specifies a shift of 0, then C is cleared; otherwise, C is
filled with the last bit to be shifted out of the ACC:P registers:
0
C
ACC:P
ACC:P
Last bit out or cleared
Discard
other bits
Left shift
contents of T (5:0)
Flags and
Modes
N After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the
N bit is set; otherwise N is cleared.
Z After the shift, the Z flag is set if the combined 64-bit value of the ACC:P is
zero; otherwise, Z is cleared.
C If (T(5:0) = 0) clear C; otherwise, the last bit shifted out of the combined 64-bit
value is loaded into the C bit.
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Logical shift left the 64-bit Var64 by contents of Var16:
MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64
MOVL P,@Var64+0 ; Load P with low 32 bits of Var64
MOV T,@Var16 ; Load T with shift value from Var16
LSL64 ACC:P,T ; Logical shift left ACC:P by T(5:0)
MOVL @Var64+2,ACC ; Store high 32-bit result into Var64
MOVL @Var64+0,P ; Store low 32-bit result into Var64
To Next Page
Loading...
Need help?
General
