LSRL ACC,T
6-144
LSRL ACC,T Logical Shift Right by T (4:0)
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
LSRL ACC,T 0101 0110 0010 0010 1 − 1
Operands ACC Accumulator register
T Upper 16 bits of the multiplicand (XT) register
Description Perform an logical shift right on the content of the ACC register as specified
by the five least significant bits of the T register, T(4:0) = 0…31. Higher order
bits are ignored. During the shift, the high order bits of ACC are zero-filled. If
T specifies a shift of 0, then C is cleared; otherwise, C is filled with the last bit
to be shifted out of the ACC register:
0
C
ACC
ACC
Right shift
Contents of T (4:0)
Discard
other bits
Last bit out or cleared
Flags and
Modes
Z After the shift, the Z flag is set if the ACC value is zero, else Z is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the zero condition and Z is affected.
N After the shift, the N flag is set if bit 31 of the ACC is 1, else N is cleared. Even
if the T register specifies a shift of 0, the content of the ACC register is still
tested for the negative condition and N is affected.
C If (T(4:0) = 0) then C is cleared; otherwise, the last bit shifted out is loaded
into the C flag bit.
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Logical shift right contents of VarA by VarB:
MOVL ACC,@VarA ; ACC = VarA
MOV T,@VarB ; T = VarB (shift value)
LSRL ACC,T ; Logical shift right ACC by T(4:0)
MOVL @VarA,ACC ; Store result into VarA
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