LSR64 ACC:P,T
6-143
LSR64 ACC:P,T 64-Bit Logical Shift Right by T(5:0)
SYNTAX OPTIONS OPCODE OBJMODE RPT CYC
LSR64 ACC:P,T 0101 0110 0101 1011 1 − 1
Operands ACC:P Accumulator register (ACC) and product register (P)
T Upper 16 bits of the multiplicand register (XT)
Description Logical shift right the 64-bit combined value of the ACC:P registers by the
amount specified by the six least significant bits of the T register,
T(5:0) = 0…63. Higher order bits are ignored. As the value is shifted, the
most significant bits are zero filled. If T specifies a shift of 0, then C is cleared;
otherwise, C is filled with the last bit to be shifted out of the ACC:P registers:
0
C
ACC:P
ACC:P
Right shift
(Contents of T(5:0)
Discard
other bits
Last bit out or cleared
Flags and
Modes
N
After the shift, if bit 31 of the ACC register is 1 then ACC:P is negative and the
N bit is set; otherwise N is cleared.
Z
After the shift, the Z flag is set if the combined 64-bit value of the ACC:P is
zero; otherwise, Z is cleared.
C If (T(5:0) = 0) clear C; otherwise, the last bit shifted out of the combined 64-bit
value is loaded into the C bit.
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
Example
; Arithmetic shift right the 64-bit Var64 by contents of Var16:
MOVL ACC,@Var64+2 ; Load ACC with high 32 bits of Var64
MOVL P,@Var64+0 ; Load P with low 32 bits of Var64
MOV T,@Var16 ; Load T with shift value from Var16
LSR64 ACC:P,T ; Logical shift right ACC:P by T(5:0)
MOVL @Var64+2,ACC ; Store high 32-bit result into Var64
MOVL @Var64+0,P ; Store low 32-bit result into Var64
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