Status Register (ST0)
2-18
Table 2−4. Instructions That Affect OVC/OVCU (Continued)
Signed Addition Instructions Effect on OVC/OVCU
MPYS P,T,loc16
QMPYSL P,XT,loc32
SBBU ACC,loc16
SQRS loc16
SUB ACC,#16bit << shift
SUB ACC,loc16 << shift
SUB ACC,loc16 << T
SUBB ACC,#8bit
SUBBL ACC,loc32
SUBL ACC,loc32
SUBL loc32,ACC
SUBRL loc32,ACC
SUBU ACC,loc16
SUBUL ACC,loc32
SUBUL P,loc32
Unsigned Instructions Effect on OVC/OVCU
ADDUL ACC,loc32 Inc OVC/OVCU on unsigned carry
ADDUL P,loc32
IMPYAL P,XT,loc32
IMACL P,loc32,*XAR7/++
Misc Instructions Effect on OVC/OVCU
SAT ACC if(OVC > 0) Saturate +ve
if(OVC < 0) Saturate −ve
OVC = 0
SAT64 ACC:P
ZAPA OVC = 0
ZAP OVC
MOV OVC,loc16 OVC = [loc16(15:10)]
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