Status Register (ST0)
2-19Central Processing Unit
Table 2−4. Instructions That Affect OVC/OVCU (Continued)
Signed Addition Instructions Effect on OVC/OVCU
MOVU OVC,loc16 OVC = [loc16(5:0)]
Condition Operation Performed by SAT ACC Instruction
OVC = 0
Leave ACC and OVC unchanged.
OVC > 0
Saturate ACC in the positive direction (fill ACC with 7FFFFFFF
16
), and clear OVC.
OVC < 0
Saturate ACC in the negative direction (fill ACC with 80000000
16
), and clear OVC.
PM
Bits 9−7
Product shift mode bits. This 3-bit value determines the shift mode for any output opera-
tion from the product (P) register. The shift modes are shown in the following table. The out-
put can be to the ALU or to memory. All instructions that are affected by the product shift
mode will sign extend the P register value during a right shift operation. At reset, PM is
cleared (left shift by 1 bit is the default).
PM is summarized as follows:
000 Left shift by 1. During the shift, the low-order bit is zero filled. At reset, this mode
is selected.
001 No shift
010 Right shift by 1. During the shift, the lower bits are lost, and the shifted value is sign
extended.
011 Right shift by 2. During the shift, the lower bits are lost, and the shifted value is sign
extended.
100 Right shift by 3. During the shift, the lower bits are lost, and the shifted value is sign
extended.
101 Right shift by 4. During the shift, the lower bits are lost, and the shifted value is sign
extended.
Note, if AMODE = 1, then 101 is a left shift by 4.
110 Right shift by 5. During the shift, the lower bits are lost, and the shifted value is sign
extended.
111 Right shift by 6. During the shift, the lower bits are lost, and the shifted value is sign
extended.
Note: For performing unsigned arithmetic, you must use a product shift of 0 (PM = 001) to avoid sign extension and genera-
tion of incorrect results.
Table 2−5 lists instructions that are affected by the PM bits. See the instruction
set in chapter 6 for a complete description of each instruction.
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