TRAP #VectorNumber
6-364
Part of the operation involves saving pairs of 16-bit core registers onto the
stack pointed to by the SP register. Each pair of registers is saved in a single
32-bit operation. The register forming the low word of the pair is saved first
(to an even address); the register forming the high word of the pair is saved
next (to the following odd address). For example, the first value saved is the
concatenation of the T register and the status register ST0 (T:ST0). ST0 is
saved first, then T.
This instruction should not be used with vectors 1−12 when the peripheral
interrupt expansion (PIE) is enabled.
Note: The TRAP #0 instruction does not initiate a full reset. It only forces execution of the
interrupt service routine that corresponds to the RESET interrupt vector.
Flush the pipeline;
temp = PC + 1;
Fetch specified vector;
SP = SP + 1;
[SP] = T:ST0;
SP = SP + 2;
[SP] = AH:AL;
SP = SP + 2;
[SP] = PH:PL;
SP = SP + 2;
[SP] = AR1:AR0;
SP = SP + 2;
[SP] = DP:ST1;
SP = SP + 2;
[SP] = DBGSTAT:IER;
SP = SP + 2;
[SP] = temp;
INTM = 0; // disable INT1−INT14, DLOGINT, RTOSINT
DBGM = 1; // disable debug events
EALLOW = 0; // disable access to emulation registers
LOOP = 0; // clear loop flag
IDLESTAT = 0; // clear idle flag
PC = fetched vector;
Flags and
Modes
DBGM
Debug events are disabled by setting the DBGM bit.
INTM
Setting the INTM bit disables maskable interrupts.
EALLOW
EALLOW is cleared to disable access to protected registers.
LOOP
The loop flag is cleared.
IDLESTAT
The idle flag is cleared.
Repeat This instruction is not repeatable. If this instruction follows the RPT
instruction, it resets the repeat counter (RPTC) and executes only once.
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