G-7Glossary
direct addressing modes: The addressing modes that access data space
as if it were 65 536 separate blocks of 64 words each. DP direct address-
ing mode uses the data page pointer (DP) to select a data page from 0
to 65 535. PAGE0 direct addressing mode uses data page 0, regardless
of the value in the DP.
discontinuity: See program-flow discontinuity.
DLOGINT: See data log interrupt (DLOGINT).
DP: See data page pointer (DP).
DP direct addressing mode: A direct addressing mode that uses the data
page pointer (DP) to select a data page from 0 to 65 535. See also
PAGE0 direct addressing mode.
DRAB: See data-read address bus (DRAB).
DRDB: See data-read data bus (DRDB).
DT−DMA: See debug-and-test direct memory access (DT-DMA).
DWAB: See data-write address bus (DWAB).
DWDB: See data-/program-write data bus (DWDB).
E
E phase: See execute (E) phase.
EALLOW bit: See emulation access enable (EALLOW) bit.
EMU0 and EMU1 pins: Pins known as the TI extensions to the JTAG inter-
face. These pins can be used as either inputs or outputs and are avail-
able to help monitor and control an emulation target system that is using
a JTAG interface.
emulation access enable (EALLOW) bit: A bit in status register ST1 that
enables (EALLOW = 1) or disables (EALLOW = 0) access to the emula-
tion registers. The EALLOW instruction sets the EALLOW bit, and the
EDIS instruction clears the EALLOW bit.
emulation logic: The block of hardware in the core that is responsible con-
trolling emulation activities such as data logging and switching among
debug execution states.
emulation registers: Memory-mapped registers that are available for con-
trolling and monitoring emulation activities.
Glossary
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