enable bit: See interrupt enable bits.
execute an instruction: Take an instruction from the decode 2 phase of the
pipeline through the write phase of the pipeline.
execute (E) phase: The seventh of eight pipeline phases an instruction
passes through. In this phase, the CPU performs all multiplier, shifter,
and arithmetic-logic-unit (ALU) operations. See also pipeline phases.
extended auxiliary registers: See XAR6/XAR7.
F
F1 phase: See fetch 1 (F1) phase.
F2 phase: See fetch 2 (F2) phase.
FC : See fetch counter (FC).
fetch 1 (F1) phase: The first of eight pipeline phases an instruction passes
through. In this phase, the CPU places on the program-read bus the ad-
dress of the instruction(s) to be fetched. See also pipeline phases.
fetch 2 (F2) phase: The second of eight pipeline phases an instruction
passes through. In this phase, the CPU fetches an instruction or instruc-
tions from program memory. See also pipeline phases.
fetch counter (FC) : The register that contains the address of the instruction
that is being fetched from program memory.
field : See bit field.
H
hardware interrupt: An interrupt initiated by a physical signal (for example,
from a pin or from the emulation logic). See also software interrupt.
hardware interrupt priority: A priority ranking used by the CPU to deter-
mine the order in which simultaneously occurring hardware interrupts
are serviced.
hardware reset: See reset.
high addresses: Addresses closer to 3F FFFF
16
than to 00 0000
16
. See
also low addresses.
high bits: See MSB.
Glossary
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