G-9Glossary
high word: The 16 MSBs of a 32-bit value. See also low word.
host processor: The processor running the user interface for a debugger.
I
IC: See instruction counter (IC).
IDLESTAT (IDLE status) bit: A bit in status register ST1 that indicates when
an IDLE instruction has the CPU in the idle state (IDLESTAT = 1).
idle state: The low-power state the CPU enters when it executes the IDLE
instruction.
IEEE 1149.1 standard: “IEEE Standard Test Access Port and Boundary-
Scan Architecture”, first released in 1990. See also JTAG.
IER: See interrupt enable register (IER).
IFR: See interrupt flag register (IFR).
illegal instruction: An unacceptable value read from program memory dur-
ing an instruction fetch. Unacceptable values are 0000
16
, FFFF
16
, or any
value that does not match a defined opcode.
illegal-instruction trap: A trap that is serviced when an illegal instruction is
decoded.
immediate address: An address that is specified directly in an instruction
as a constant.
immediate addressing modes: Addressing modes that accept a constant
as an operand.
immediate constant/data: A constant specified directly as an operand of
an instruction.
immediate-constant addressing mode: An immediate addressing mode
that accepts a constant as an operand and interprets that constant as
data to be stored or processed.
immediate-pointer addressing mode: An immediate addressing mode
that accepts a constant as an operand and interprets that constant as the
16 LSBs of a 22-bit address. The six MSBs of the address are filled with
0s.
increment: To add 1 or 2 to a register or memory value. The value added
depends on the circumstance. For example, if you use the operand
*AR4++, the auxiliary register AR4 is incremented by 1 for a 16-bit opera-
tion and by 2 for a 32-bit operation.
Glossary
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