ready signals: When the core requests a read from or write to a memory
device or peripheral device, that device can take more time to finish the
data transfer than the core allots by default. Each device must use one
of the core’s ready signals to insert wait states into the data transfer when
it needs more time. Wait-state requests freeze a portion of the pipeline
if they are received during the fetch 1, read 1, or write pipeline phase of
an instruction.
real-time mode: An emulation mode that enables you execute certain inter-
rupts (time-critical interrupts), even when the CPU is halted. See also
stop mode.
real-time operating system interrupt (RTOSINT): A maskable hardware
interrupt generated by the emulation hardware in response to certain de-
bug events. This interrupt should be disabled in the interrupt enable reg-
ister (IER) and the debug interrupt enable register (DBGIER) unless
there is a real-time operating system present in your debug system.
reduced instruction set computer (RISC): A computer whose instruction
set and related decode mechanism are much simpler than those of mi-
croprogrammed complex instruction set computers.
register addressing mode: An addressing mode that enables you to refer-
ence registers by name.
register conflict: A pipeline conflict that would occur if an instruction read
a register value before that value were changed by a prior instruction.
The C28x pipeline inserts as many inactive cycles as needed between
conflicting instructions to prevent register conflicts.
register pair: One of the pairs of CPU register stored to the stack during an
automatic context save.
repeat counter (RPTC): The counter that is loaded by the RPT (repeat) in-
struction. The number in the counter is the number of times the instruc-
tion qualified by RPT is to be repeated after its initial execution.
reserved: A term used to describe memory locations or other items that you
cannot use or modify.
reset: To return the DSP to a known state; an action initiated by the reset
(RS
) signal.
return: 1) The operation of forcing program control to a return address. 2)
An instruction that performs such an operation. See also call.
return address: The address at which the CPU resumes processing after
executing a subroutine or interrupt service routine.
Glossary
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