G-19Glossary
RISC: See reduced instruction set computer (RISC).
rotate operation: An operation performed by the ROL (rotate accumulator
left) or ROR (rotate accumulator right) instruction. The operation, which
involves a shift by 1 bit, can be seen as the rotation of a 33-bit value that
is the concatenation of the carry bit (C) and the accumulator (ACC).
RPTC: See repeat counter (RPTC).
RTOSINT : See real-time operating system interrupt (RTOSINT).
RUN command : A debugger command used to execute all or a portion of
a program. The RUN 1 command causes the debugger to execute a
single instruction.
run state: A debug execution state. In this state, the CPU is executing code
and servicing interrupts freely. See also debug-halt state and single-in-
struction state.
S
select signal: An output signal from the C28x that can be used to select spe-
cific memory or peripheral devices for particular types of read and write
operations.
scan controller: A device that performs JTAG state sequences sent to it by
a host processor. These sequences, in turn, control the operation of a tar-
get device.
service an interrupt : The CPU services an interrupt by preparing for and
then executing the corresponding interrupt service routine. See also in-
terrupt request and approve an interrupt request.
set: To set a bit is to write a 1 to it. If a bit is set, it contains 1. See also clear.
sign extend: To fill the unused most significant bits (MSBs) of a value with
copies of the value’s sign bit.
sign-extension mode (SXM) bit: A bit in status register ST0 that enables
or suppresses sign extension. When sign-extension is enabled
(SXM = 1), operands of certain instructions are treated as signed and
are sign extended during shifting.
single-instruction state: A debug execution state. In this state, the CPU
executes one instruction and then returns to the debug-halt state. See
also debug-halt state and run state.
Glossary
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