General Purpose Digital I/O
TMS320F2837xD Microcontroller Workshop - System Initialization 5 - 13
F2837xD GPIO Pin Block Diagram
GPxDAT(W)
GPxSET
00:00
00:01
00:10
00:11
01:00
01:01
01:10
01:11
10:xx
11:xx
Peripheral 1
Peripheral 2
Peripheral 3
GPIO
GPIO & Peripherals 9-11
Peripheral 5
Peripheral 6
Peripheral 7
GPIO
GPIO & Peripherals 13-15
00:00
00:01
00:10
00:11
01:00
01:01
01:10
01:11
10:xx
11:xx
Peripheral 1
Peripheral 2
Peripheral 3
unused
Peripherals 9-11
Peripheral 5
Peripheral 6
Peripheral 7
Peripherals 13-15
unused
GPxGMUX1/2
GPxMUX1/2
GPxG:GPx
00
01
10
11
GPxDAT(W
)
GPxSET
CPU1
CPU1.CLA
CPU2
CPU2.CLA
Input
X-BAR
GPxCSEL1-4
Pin
Internal Pull-Up
0 = enable
1 = disable
(default GPIO 0-xx)
GPxPUD
0 = Input
1 = Output
GPxDIR
Input
Qualification
GPxINV
GPxQSEL1/2
GPxCTRL
0 1
GPxDAT(R)
CPU1
GPxDAT(R)
CPU1.CLA
GPxDAT(R)
CPU2
GPxDAT(R)
CPU2.CLA
x = A, B, C, D, E, or F
CPU1
CPU1
CPU1
CPU1
CPU1
CPU1
GPxODR
CPU1
0 = Normal
1 = Open Drain
The input qualification scheme is very flexible, and the type of input qualification can be
configured for each GPIO pin individually. In the case of a GPIO input pin, the qualification can
be specified as only synchronize to SYSCLKOUT or qualification by a sampling window. For pins
that are configured as peripheral inputs, the input can also be asynchronous in addition to
synchronized to SYSCLKOUT or qualified by a sampling window.
F28x7x GPIO Input Qualification
Qualification available on ports A - F
Individually selectable per pin
no qualification (peripherals only)
sync to CPUx.SYSCLK only
qualify 3 samples
qualify 6 samples
Input
Qualification
pin
to GPIO and
peripheral
modules
CPUx.SYSCLK
T
T T
samples taken
T = qual period
To Next Page
Loading...
Need help?
General
