PCWS 2015 Setup Guide - 2nd Edition 3-23
What’s Inside?
System Board Technical Description
System Board Technical Description
The available PCWS 2015 Processors are based on the low power-high
performance 45nm Nehalem micro-architecture, and consists of a two-chip
platform.
The two-chip platform consists of the Processor and Platform Controller Hub
(PCH) a configuration that enables higher performance, lower cost, and
smaller footprint.
The Processor integrates the Intel HD Graphics Engine and Integrated Memory
Controller on the same package as the processor core. This is known as a
multi-chip package (MCP) processor. In Figure 3-24 below, the processor core
is housed in the larger of the two packages.
Figure 3-24: Celeron P4505 or i5-520 Processor Multi-Chip Package
Intel i5 General Features
• Two execution cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core.
• A 256-KB shared instruction/data second-level cache (L2) for each core.
• Up to 4-MB shared instruction/data third level cache (L3), shared among
all cores.
• Thermal Management via TM1 and TM2.
Supported Technologies
o Intel Virtualization Technology (Intel VT-x).
o Intel Virtualization Technology for Directed I/O (Intel VT-d).
To Next Page
Loading...