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Micros Systems PCWS 2015 - Gpio; Lpc; Smbus

Micros Systems PCWS 2015
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3-28 PCWS 2015 Setup Guide - 2nd Edition
What’s Inside?
System Board Technical Description
The PCWS 2015 System Board uses a Realtek ALC268-VB1 HD Audio
Codec. Like the WS5/WS5A case work on which it based, the PCWS 2015
includes two speakers mounted to the left and right side of the base. A two
watt per channel amplifier drives the speakers. In addition, the PCWS 2015
includes Microphone Input and Line Output connectors on the I/O Panel.
GPIO
General Purpose IO signals are used to activate IDN Port Control, provide
selectable voltages to the powered USB and RS232 ports, manage the
recovery button and last state flip-flops among other items.
Most the GPIO signals on PCWS 2015 Revision C System Board originate
from the CPLD, U22. On the Revision D System Board, many of the
additional GPIO lines required to manage the USB port switching and
voltage control are supplied by the the QM57.
LPC
The QM57 implements an LPC interface based on the Low Pin Count
Interface Specification Revision 1.1.
On the PCWS 2015 System Board, several devices are connected to the
LPC Bus.
CPLD U22, and Super IO U15 are the primary devices on this bus in
addition to LPC Debug Port, J8.
SMBus
The System Management Bus is compatible with System Management Bus
Specification, Version 2.0.
The QM57 contains an SMBus Host interface that allows the processor to
communicate with SMBus Slaves. This interface is compatible with most
I2C devices. Special I2C commands are implemented.
The SMBus also implements hardware based Packet Error Checking for
data robustness and the Address Resolution Protocol (ARP) to dynamically
provide addresses to all SMBus devices.

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