Motorola MPC823e - Page 1025

LCD Controller
18-28 MPC823e REFERENCE MANUAL MOTOROLA
LCD CONTROLLER
18
18.4.5 LCD Frame Buffer B Start Address Register
The 32-bit LCD frame buffer B start address (LCFBA) register contains the start address of
the frame buffer data that you want to send to your LCD dual-scan panel (lower half). FIFO
B is the destination for your frame buffer data to be passed to the lower half of the panel.
Notice that for single-scan panels, FIFO B is concatenated with FIFO A to transfer data, so
only the LCFAA register needs to be loaded. However, for dual-scan panels, the LCFBA
register must be set. For dual-scan panels, the DMA controller uses the buffer B start
address to initiate data transfers from display memory (system memory or a dedicated
display memory block) to FIFO B. Because all LCD controller DMA bursts must be 16-byte
aligned, the four least-significant bits of the address are not used. This register is read by
the LCD controller at the start of each frame. Therefore, changing this register will not take
effect until the WBF bit expires.
FBA—FIFO B Address
This field designates the start address in display or system memory where the LCD panel
data resides. The data retrieved is for the lower half of a dual-scan panel and passes
through FIFO B.
LCFBA
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD FBA
RESET —
R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x854
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD FBA X
RESET ——
R/W R/W R/W
ADDR
IMMR & 0xFFFF0000 + 0x856
NOTE: X - “Don’t Care” and — = Undefined.