Motorola MPC823e - Page 1046

Video Controller
19-12 MPC823e REFERENCE MANUAL MOTOROLA
VIDEO CONTROLLER
19
19.3.7 Video Frame Buffer B Start Address Register (Set 0)
The 32-bit video frame buffer B start address register set 0 (VFBA0) holds the start address
of the set_0 even field. Since all bursts must be 16-byte aligned, this register does not use
the four least-significant bits of the address.
FBA0—Frame Buffer B Start Address for Set 0
This field designates the start address of the frame buffer B set 0 in system memory.
VFBA0
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD FBA0
RESET —
R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0x818
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD FBA0 X
RESET ——
R/W R/W R/W
ADDR (IMMR & 0xFFFF0000) + 0x81A
NOTE: X = “Don’t Care” and — = Undefined.