Video Controller
MOTOROLA
MPC823e REFERENCE MANUAL
19-11
VIDEO CONTROLLER
19
NBPL0—Number of Bursts per Line 0
This field defines the number of bursts per line.
19.3.6 Video Frame Buffer A Start Address Register (Set 0)
Th 32-bit video frame buffer A start address register set 0 (VFAA0) holds the start address
of the set_0 odd field. Since all bursts must be 16-byte aligned, this register does not use
the four least-significant bits of the address.
FAA0—Frame Buffer A Start Address for Set 0
This field designates the start address of the frame buffer A set 0 in system memory.
Note:
The value of the NBPL0 field must be non-zero or an error will occur.
VFAA0
BIT
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
FAA0
RESET
—
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0x814
BIT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
FAA0 X
RESET
——
R/W
R/W R/W
ADDR
(IMMR & 0xFFFF0000) + 0x816
NOTE: X = “Don’t Care” and — = Undefined.
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